Senior Silicon Manufacturing Methodology Engineer

Silicon Co-Design Group (SCG) is a wide-ranging, multi-functional, integral team at NVIDIA. We sit at the crossroads of design, architecture, marketing, operations, and productization. Our contributions span from the arch stage and extend to defining final products. We architect innovative solutions for Datacenter, Server, Gaming, Robotics, Automotive, and Embedded markets. We are fast-paced, dynamic, share a sense of humor, and collaborate extensively to push the boundaries of what is possible. We do all of this with an eye on making groundbreaking, impactful market disruptions! We are looking for a Senior Silicon Manufacturing Methodology Engineer to define and implement the validation and screening of new silicon features within high-volume manufacturing flows. You will translate product requirements into executable test methodologies, infrastructure, and detailed manufacturing test plans that ensure quality, yield, and efficiency at scale. This role sits at the intersection of multiple cross-functional teams to make manufacturing test an outstanding part of the overall codesign and DFP (Design for Productization) lifecycle. This is a highly visible, multi-functional role focused on building DFP methodologies that help products meet SOL milestones and achieve the high NVIDIA quality bar our customers expect. Success in this role requires turning hard manufacturing and test problems into reusable methods, better decisions, and stronger production roadmaps.

Own end-to-end manufacturing methodology strategy, defining organization-wide standards adopted across teams, products, and future generations, and shaping how manufacturing issues are screened, debugged, and closed. Translate system specs and product POR into DFP requirements, test content, coverage, flows, and testability requirements, and maintain the DFP roadmap across infrastructure planning, execution readiness, and sign-off alignment. Partner multi-functionally to implement test content, debug hooks, and screening improvements, and drive alignment on manufacturability, test time, binning strategies, and cost-versus-coverage trade-offs. Turn incomplete yield, coverage, and correlation issues into hypothesis trees, measurement plans, and executable paths to closure. Define data and analytics frameworks to support yield analysis ,anomaly detection, and continuous improvement. Lead methodology strategy and DFP documentation as the single source of truth and feed findings into future methodologies , reusable methods, and production decisions. Create production-standard test methods, analytics systems, and debug frameworks that become durable artifacts adopted by engineering teams across products and future generations. Build secure, traceable, and validated AI-assisted workflows for analysis, debug, documentation, and methodology automation, with human oversight for critical engineering judgments. What we need to see: BS/MS in Electrical Engineering, Computer Engineering, or related field (or equivalent experience) 8+ years in silicon post‑silicon validation and/or high‑volume manufacturing test for complex SoCs, GPUs, CPUs, or similar. Hands‑on experience with test content bring‑up, limit setting, correlation to characterization, and yield/coverage optimization, and prior ownership of manufacturing test strategy from early planning through ramp to QS/production. Proficiency with scripting and data analysis (e.g., Python, MATLAB, R, SQL) for test data analytics, limit tuning, and yield/debug analysis. Demonstrated ability to frame ambiguous manufacturing problems, define evidence-driven trade-offs, and drive cross-functional alignment and closure around plans, dependencies, and sign-off criteria. Excellent communication skills and comfort authoring structured technical documents and test plans used by global manufacturing and validation teams. Strong AI-enabled skills and thinking, using AI to accelerate analysis, exploration, and