CPU Execution Unit Design and Micro-Architect Engineer

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits Learn more about benefits at Google .

Create the first Google CPU for processor design team. Define floating point data paths implementing the IEEE 754 standard while achieving performance, clock and low power goals. Implement integer single instruction, multiple data (SIMD) and floating point SIMD data paths focusing on power/performance. Work with architecture teams and other micro architects to define high performance floating point issue, register, bypass and retirement logic to support a complex FP-SIMD instruction set architecture (ISA).

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 4 years of experience with IEEE 754 datapath implementations including design, verification and physical implementation issues. Experience with Floating Point and SIMD ISA. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. 4 years of experience in high-performance floating point datapath design. Understanding of design techniques to minimize data path power usage. Understanding of data path design techniques to achieve high clock rates.