ASIC/FPGA Design Verification Engineer, Senior Staff

Company: Qualcomm Canada ULC Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path. New Position. Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. What You’ll Do            Deliver standards-compliant IP blocks or subsystems for use in PCIe Gen7 (and beyond) and CXL 4.0 (and beyond) FPGAs or ASICs. Lead ASIC or FPGA projects. Lead verification of IP block or subsystem. Streamline ASIC development process with advanced tools, AI-based approaches and scripts. Develop verification test plan. Architect, develop and document verification environments based on SystemVerilog and UVM. Develop and debug test cases against the RTL to complete the test plan. Issue and track bug reports from inception to closure. Develop script to augment development process. Mentor junior engineers. What You’ll Need Msc/MEng with 7+ years of experience, or BSc/Beng with 10+ years of experience in ASIC or FPGA development. Strong communications Protocol Knowledge (PCIe, CXL, UALink, Ethernet). Deep experience and knowledge of SystemVerilog, UVM and Constrained Random – Coverage Driven methodologies. Strong experience with simulation tools. Strong experience with Unix/Linux Shell scripting and source code revisioning systems. It’d Be Amazing If You Had Experience in PCIe Gen5/6/7 or CXL 3.0/4.0 Physical Layer to Transaction Layer protocols. Experience in using PCIe/CXL VIP from Siemens/Avery, Cadence or Synopsys. Experience in using AI-based approaches to streamline various phases of verification flow. Experience in Perl, Python and TCL scripting.

Excellent communication skills. Able to listen to and appreciate ideas and opinions that differ from yours. Extremely detail oriented. Superb analytical and problem-solving skills. Drives for consistency. Takes personal pride in high standard of outputs. Self-motivated and self-managing. Mentoring and coaching skills. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail  disability-accomodations@qualcomm.com  or call Qualcomm's toll-free number found  here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary