RFIC Design Engineer

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > RFIC Design General Summary: Define, design and develop complex radio frequency integrated circuits in complex SoC’s and discrete RFIC’s. Perform radio signal path and circuit topology analysis and detailed transistor-level design of highly-integrated transceivers and associated blocks for wireless applications, 4G, 5G, 6G, WLAN, BT and GPS standards using advanced process technologies. Utilize complex analysis, simulation, engineering, science and mathematical principles to compose algorithm structures to solve problems. Assess processing requirements and select devices to meet requirements. Debug and assess performance of algorithms in actual application hardware.    Preferred Qualifications: •    3+ years experience in the transistor level design of RF analog integrated circuits with a Master's degree in Electrical Engineering. •    Ph.D. in Electrical Engineering with internship or publication. •    3+ years of experience in one or more of the following areas: Design of receiver and transmitter RF/Analog circuits, Design of high-performance RF frequency synthesizers, Digital control and signal processing, Product experience from conception, design, and product commercialization, Electro Magnetic simulation/modeling. •    1+ year of experience working in a large matrixed organization.   •    1+ year of work experience in a role requiring interaction with senior leadership (e.g., Director and above).   Principal Duties and Responsibilities: •    Determines circuit-level specifications based on system-level requirements with minimal supervision. •    Uses technical expertise with tools/applications to develop the architecture and design of one or more blocks based on specifications.  •    Resolves architecture and design problems by applying sound RFIC engineering practices with minimal supervision.  •    Runs simulations to determine how circuits perform under various circumstances with minimal supervision. •    Independently floor-plan layout; works with layout engineers under minimal guidance to generate the layout of circuits and conduct physical verification on the layout; participate in review of generated layout. •    Writes test plans and reviews test results to assess performance and identify any bugs in own work and provides instructions to test engineers for their design block. •    Debugs most issues and escalates highly complex issues.  Use of Neural Networks for circuit optimization and analysis. •    Seeks essential knowledge of industry trends, and advances related to RFICs. •    Collaborates with team members to generate new ideas. •    Writes clear and detailed technical documentation and feature descriptions to guide users.      Level of Responsibility: •    Working under close supervision. •    Taking responsibility for own work and making decisions with limited impact; impact of decisions is readily apparent; errors made typically only impact timeline (i.e., require additional time to correct). •    Using verbal and written communication skills to convey basic, routine factual information about day-to-day activities to others who are fully knowledgeable in the subject area. •    Working within prescribed budget and resources. •    Having a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to provide input on key decisions). •    Completing some tasks with multiple steps which must be performed in a specific order; directions or manuals can accurately document the steps necessary to perform the task. •    Exercising some creativity to troubleshoot technical problems or deal with novel circumstances. •    Using deductive and inductive problem solving; multiple approaches may be taken/necessary to solve the problem; often