Design Verification Engineering Intern - MS/PhD

We can't predict what the future holds, but we know Texas Instruments will have a part in shaping it. As a Design Verification intern in this group, you will be responsible for:

Developing detailed verification plans while working closely with the design and system team to ensure pre- silicon verification success Developing test benches, tests and simulations to DUT behavior Running coverage regressions to meet the defined coverage goals for SystemVerilog functional coverage models of mixed-signal circuits for voltages and currents, real numbers, integers, and traditional digital functional coverage. Tracking and communicating verification status, issues, and concerns Work with regression tools and develop scripts to submit cases for regression analysis Utilize RTL and Gates+SDF, including verifying chip-level timing between analog and digital circuits. Constrained-random stimulus and auto-checking verification environments, especially constrained-random analog stimulus. Contribute to continuous improvements for quality and efficiency on DV strategy, tools, methods and flows

Put your talent to work with us as a Design Engineer Intern – change the world, love your job!