Principal Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

BE/BTECH/ME/MTECH Or Equivalent Degree EXP-7-15years Key Responsibilities Perform static/dynamic IR-drop  and EM analysis  using tools like RedHawk‑SC and Voltus.  Drive IREM fixes  during PnR and PV signoff cycles.  Optimize full‑chip and block‑level Power Delivery Network (PDN) , including PG mesh and RDL structures. Develop automation scripts (TCL/Python/Perl/Shell) to improve signoff efficiency and reduce TAT.  Collaborate with cross‑functional teams to resolve IR hot spots, EM‑violating nets, and PG bottlenecks.

7+ years in IR/EM/PDN signoff across 7nm → 3nm nodes. Hands‑on expertise with Voltus/Redhawk‑SC , Innovus/ICC2 environments.  Strong scripting and automation background. Understanding of placement, routing, congestion, timing ECOs, and how they impact PG integrity.  We’re doing work that matters. Help us solve what others can’t.