ASIC Physical Design, Staff Engineer

Descriptions & Requirements

Job Description and Requirements

Alternate Job Titles Physical Design Engineer, Staff Level ASIC Implementation Engineer, Staff Staff Engineer, PnR and Signoff Senior Physical Design Engineer, ASIC We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical design, turning RTL into silicon that actually closes, meets timing, and ships. The difference between a design that tapes out clean and one that needs three more spins is something you can see coming in the floorplan stage, and you are the kind of engineer who makes the call early, adjusts the plan, and keeps the project moving. You are comfortable owning the full physical implementation flow from synthesis through signoff. When a timing path refuses to close or an IR drop issue surfaces late in the cycle, you do not escalate first, you dig in, trace it back, and solve it. You know the tools deeply, Fusion Compiler, PrimeTime, StarRC, IC Validator, and you use them with intention, not just by rote. Working across teams comes naturally to you. Front-end hands you an RTL block, analog gives you constraints that shift midstream, CAD updates the flow, and you synthesize all of it into a coherent implementation without losing your thread or your timeline. You mentor others not by lecturing but by showing them how you think through a problem. At Synopsys, you will work on mixed-signal IP that powers real products, with a team that values both technical depth and the ability to ship.

Lead physical implementation of high-speed interface IPs from RTL through GDSII, managing floorplanning, placement, CTS, routing, and signoff closure Drive timing closure using PrimeTime, resolving setup and hold violations across multiple corners and modes in advanced process nodes Execute power integrity analysis using RedHawk or Voltus, ensuring IR drop and electromigration compliance Collaborate with front-end, analog design, CAD, and product teams to integrate IP blocks and resolve interface issues Mentor engineers on physical design best practices, debug strategies, and methodology improvements The Impact You Will Have Deliver high-performance mixed-signal IP that meets aggressive timing, power, and area targets for next-generation SoCs Enable faster time-to-market for Synopsys customers by ensuring robust, signoff-clean physical implementations Raise the technical capability of the physical design team through hands-on mentorship and knowledge sharing Drive methodology improvements that reduce design cycle time and increase first-pass success rates Support the adoption of advanced process nodes by solving complex physical design challenges in 7nm, 5nm, and below What You'll Need Bachelor's or Master's degree in Electrical Engineering with 8+ years of hands-on physical design experience in ASIC or IP development Deep expertise in the full physical design flow from RTL to GDSII, including synthesis, place and route, and physical signoff Proficiency with Synopsys physical design tools such as Fusion Compiler, IC Compiler II, PrimeTime, StarRC, and IC Validator Strong understanding of advanced node challenges including finFET effects, multi-patterning, and low-power design techniques Proven ability to close timing, power, and signal integrity on complex mixed-signal designs in 16nm or below Who You Are You make decisions with incomplete information, prioritize what matters, and adjust course when new data arrives without losing momentum You can explain a timing violation or power integrity issue to different audiences and