Graduate – Analog Design Engineer

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Key responsibilities in your new role Circuit Design: Design and refine analog/mixed-signal blocks including op-amps, comparators, bandgaps, LDOs, charge pumps, bias generators, and ADC/DAC subcircuits at the transistor level Control Loop Design: Design and verify DC-DC control loops for compensation, transient response, EMI/EMC, efficiency optimization, startup/soft start, and protection features (UVLO, OCP, OVP, OTP) Simulation Tasks: Execute SPICE simulations covering DC/AC/transient analysis, stability, PSRR/CMRR, PVT corners, Monte Carlo mismatch/yield studies, and parasitic-aware post-layout verification Layout Collaboration: Partner with layout engineers on device matching, common centroid techniques, guard rings, isolation, shielding, routing strategy, and physical verification (DRC, LVS, PEX) Top-Level Integration: Integrate analog blocks into chip-level designs with attention to biasing, I/O pad ring ESD, power domains, and startup/reset sequencing in coordination with digital/mixed-signal teams Silicon Bring-Up: Support ATE/test engineering with characterization vectors and limit setting while contributing to yield ramp investigations and post-silicon correlation Cross-Functional Support: Collaborate with Systems, Applications, Reliability, Packaging, and Test/Production teams to translate system requirements into circuit specifications and ensure DfT compliance Your profile Qualifications and skills to help you succeed Education: Graduating Spring 2027 with a MS or PhD in Electrical Engineering Design Experience: Hands-on experience with transistor-level analog/mixed-signal circuit design including LDOs, switching regulators, bandgap references, op-amps, or gate drivers through coursework or thesis work Simulation Proficiency: Proficiency in SPICE-based simulation tools (Cadence Spectre, HSPICE, or equivalent) with exposure to behavioral modeling using Verilog-A or MATLAB Semiconductor Knowledge: Familiarity with CMOS and/or BCD process technologies including high-voltage device handling, ESD/latch-up constraints, and reliability considerations (BTI, HCI, EM) Layout Awareness: Basic understanding of analog layout techniques including device matching, parasitic extraction (PEX), and physical verification flows (DRC, LVS) Problem-Solving: Methodical, data-driven approach to debugging with high attention to detail and the ability to correlate simulation results with silicon measurements Collaboration Skills: Strong communicator with a collaborative mindset, capable of proactively syncing across cross-functional teams including design, test, reliability, and applications · Find out what we are looking for in your CV · Find out how the student application process works with us · Discover our student website Additional information Infineon Technologies is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), gender identity, national origin, ancestry, citizenship, age, physical or mental disability, legally protected medical condition, family care status, military or veteran status, marital status, domestic partner status, sexual orientation, or any other basis protected by local, state, or federal laws. Employment at Infineon is contingent upon proof of your legal right to work in the United States under applicable law, verification of satisfactory references, successful completion of a background check and drug test, and signing all your on-boarding documents. In some instances, if applicable, U.S. export control laws require that Infineon obtain a