Midcore Design Verification Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Tenstorrent is looking for a Mid Core Design Verification Engineer to help verify the next generation of high-performance RISC-V CPU cores. You’ll work closely with CPU architects, RTL designers, and software engineers to develop verification strategies, build robust test environments, and uncover the corner cases that matter in a modern out-of-order processor. This is a hands-on role where you’ll have the opportunity to own meaningful portions of the verification effort—from developing test plans and architecting test benches to debugging failures and driving issues to closure.

This role is remote, based out of North America or Spain.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

• A hands-on verification engineer who enjoys understanding how CPUs work and finding the bugs others miss.

• Comfortable working across architecture, microarchitecture, RTL, and verification to understand complex CPU behavior.

• A strong problem solver who can debug failures, identify root causes, and work collaboratively toward solutions.

• Organized and self-motivated, with the ability to take ownership of verification tasks while working effectively within a larger team.

• Curious about high-performance processors, RISC-V, and the challenges of verifying increasingly complex CPU designs.

What We Need

• 6+ years of experience in design verification for CPUs, SoCs, ASICs, or other complex digital designs.

• Strong experience with SystemVerilog and UVM, including testbench development, constrained-random testing, assertions, and functional coverage.

• Understanding of CPU architecture and/or microarchitecture, ideally including concepts such as pipelines, out-of-order execution, caches, load/store, branch prediction, or instruction scheduling.

• Experience debugging RTL and simulation failures using waveforms and common simulation/debug tools.

• Strong C/C++ or Python skills and the ability to work effectively with RTL designers, architects, and other verification engineers.

• Gain deep hands-on experience verifying high-performance, out-of-order RISC-V CPU cores.

• Learn how CPU microarchitecture decisions translate into RTL and how those designs are verified against architectural intent.

• Develop expertise in advanced verification techniques for complex processor pipelines and interacting subsystems.

• Work closely with CPU architects and RTL engineers to understand the full design lifecycle from specification through silicon.

• Build experience with the challenges of verifying next-generation CPUs designed for AI, HPC, and high-performance computing systems.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer