Senior SOC Verification Engineer
Microsoft
- Location
- India, Karnataka, Bangalore
- Work model
- On-Site
- Level
- Senior
- H-1B history
- 2,066 approvals (FY2023)
- Posted
- 2h ago
Skills
About this role
Overview
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Verification & Validation team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. #SCHIE #CSME Responsibilities The candidate for this position will be expected and able to complete the following responsibilities: Establish yourself as an integral member of a pre-silicon SoC verification team, owning aspects of performance verification, and aligning with architecture, design, firmware, and emulation Become knowledgeable on the overall SoC architecture, including tradeoffs that effect power and performance Develop verification strategy, test plans, requirements, environments, tools, and methodologies Apply your knowledge of performance verification principles and techniques and your judgement to write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral Run tests, correlate results with architecture, debug failures to root cause, recommend fixes Apply your growth mindset to learn and adapt in a complex and dynamic environment Engage with partners to drive continuous improvement to the architecture, design, and verification plans/collateral, and to methodology to prevent, reduce, and/or find bugs sooner, more easily, or more reliably Mentor and coach team members Apply your One Microsoft mentality to collaborate with and influence architects, logic designers, post-silicon validators, other verification engineers, and IP and tool providers Embody our culture and values Qualifications Required Qualifications: 8+ years of pre-silicon SOC or subsystem or IP verification experience. Candidate should have at least a bachelor’s in electrical, Electronics, Computer Engineering, Computer Science or a related degree OR master’s degree in electrical, Electronics, Computer Engineering, Computer Science or a related degree 6+ years of verification experience working on CPU/SOC designs 2+ years of design for debug verification experience Preferred Qualifications: 3+ years of experience as part of a CPU, SoC and/or IP development team focusing on performance Demonstrated expertise in one or more of the following: Performance verification ARM architecture CPU architecture Memory Controller/PHY IPs, DDR protocols