Staff Interface IP Verification Engineer (Pre-Silicon)

Descriptions & Requirements

Job Description and Requirements

Staff Interface IP Verification Engineer (Pre-Silicon) We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years verifying silicon that has to actually work, not just pass regression, actually work, in production systems where a protocol violation or a corner case bug can cost a customer months of schedule and millions in respins. You know that the difference between IP that ships clean and IP that comes back with errata is usually a testbench decision made six months earlier, and you are the kind of engineer who catches that gap before tapeout. You are comfortable moving between PCIe link training sequences, CXL cache coherency protocols, and DDR timing constraints without losing sight of what you are actually building: reusable verification environments that have to scale across product families and customer use cases. You do not need a perfect spec to get started. You read between the lines, ask the right questions of architects, and build coverage models that reflect real-world integration scenarios, not just checklist compliance. Debugging energizes you. Not because it is heroic, but because finding the root cause of a multi-layer protocol issue and fixing it upstream makes the difference for every team that integrates your IP downstream. You have opinions on what good UVM architecture looks like, and you are not afraid to push back when a verification plan misses the actual risk. At Synopsys, you will work on Interface IP that powers AI accelerators, data centers, and next-generation SoCs used by the world's leading semiconductor companies. The team is global, the protocols are real, and what you verify will matter.

Own end-to-end verification of complex Interface IP including PCIe, CXL, DDR, and Ethernet, from architecture review through signoff and customer release Architect and build scalable UVM-based verification environments and reusable verification IP components that work across multiple product variants and customer configurations Define verification strategies and detailed test plans by analyzing specifications, identifying protocol corner cases, and mapping coverage goals to real integration risks Develop constrained-random, coverage-driven testbenches using SystemVerilog and UVM, with a focus on protocol compliance, performance validation, and system-level interaction scenarios Drive functional coverage closure by analyzing gaps, writing targeted tests, and working with design teams to ensure all architectural intent is verified before tapeout Debug complex RTL, protocol, and system-level issues across simulators like VCS or ModelSim, using waveform analysis, assertions, and protocol monitors to isolate root cause Mentor verification engineers on UVM methodology, coverage techniques, and debugging approaches while contributing to verification infrastructure and process improvements across the team The Impact You Will Have Your verification work will directly determine the quality and reliability of Interface IP integrated into AI platforms, hyperscale data centers, and high-performance computing systems used worldwide You will reduce customer-found bugs and post-silicon errata by catching protocol violations, timing issues, and integration corner cases during pre-silicon verification Your reusable verification IP and testbench architectures will accelerate verification timelines for future product generations and reduce bring-up time for derivative designs You will influence verification methodology and best practices across the