Digital Verification Engineer - Athens or Patra, Greece

Company: Qualcomm Europe, Inc., Greek Branch Office Job Area: Engineering Group, Engineering Group > GPU ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm GPU Engineer, you may architect, design, implement, verify, and/or optimize the performance and power of GPU cores. Qualcomm Engineers collaborate with cross-functional teams to meet and exceed customer needs.

We are looking for a Digital Verification Engineer to join our GPU Hardware Design team in Greece. In this role, you will contribute to the verification of complex GPU and SoC hardware blocks and help ensure that designs meet their functional, performance, and quality requirements. You will work closely with RTL designers, architects, and other verification engineers throughout the verification lifecycle, from understanding specifications and developing verification plans through testbench implementation, regression execution, coverage closure, and debug.

Develop and maintain reusable verification environments for GPU and SoC hardware blocks. Create verification plans, test scenarios, directed tests, constrained-random tests, and functional coverage models. Develop and maintain SystemVerilog and UVM-based testbenches, including agents, drivers, monitors, sequencers, scoreboards, reference models, and functional coverage. Verify control logic, datapaths, register interfaces, FIFOs, pipelines, arbiters, and data-movement functions. Verify interfaces and protocol behavior, including AMBA AXI and AHB where applicable. Develop assertions and checks to identify design and protocol violations early. Run simulations and regressions, analyze failures, and debug issues to root cause. Collaborate with RTL designers to reproduce, isolate, and resolve functional issues. Track verification progress and contribute to coverage analysis and closure activities. Review specifications, RTL, test plans, and verification results for completeness and quality. Support continuous improvement of verification methodologies, infrastructure, and automation. Document testbench architecture, test scenarios, debug findings, and verification status.

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 2–5 years of experience in digital hardware verification or a related semiconductor engineering role. Hands-on experience with SystemVerilog and object-oriented programming concepts. Practical experience with the UVM verification methodology. Understanding of standard digital verification methodologies, including verification planning, constrained-random testing, assertions, scoreboards, functional coverage, code coverage, and regression management. Understanding of digital design fundamentals, synchronous logic, finite-state machines, pipelining, FIFOs, arbitration, clocking, and reset behavior. Familiarity with simulation, waveform debugging, and common RTL verification flows. Ability to analyze technical specifications and convert them into effective verification scenarios. Strong analytical, debugging, communication, and teamwork skills.

Prior work or academic/project experience involving CPU or GPU designs. Experience with memory controller designs or memory-subsystem verification. Experience with DMA engines, data-movement architectures, or high-throughput interfaces. Knowledge of AMBA protocols, particularly AXI and AHB. Experience developing SystemVerilog Assertions and protocol checkers. Familiarity with C/C++, Python, Perl, or Tcl for test generation, automation, and analysis. Understanding of formal verification, emulation, FPGA prototyping, or silicon validation is an advantage. Exposure to industry-standard EDA tools for simulation, coverage,