Senior Staff Engineer, Data Center Interconnect Standards & Ecosystem

Company: Qualcomm China Job Area: Engineering Group, Engineering Group > Technical Standards Engineering General Summary: We are seeking a Senior Staff Engineer to drive Qualcomm’s standards, ecosystem, and industry engagement activities in AI infrastructure and data center interconnect technologies. The role spans scale-up, scale-out, scale-across, and die-to-die connectivity , covering high-speed SerDes, protocol architectures, electrical and optical interconnects, and emerging chiplet technologies. Knowledge of advanced packaging and optical integration is highly desirable .

Represent Qualcomm in relevant standards organizations and industry forums, including ODCC, CCSA, GCC, OCTC, NIDA, and other data center and AI infrastructure initiatives.  Drive technical analysis, standards development, technical contributions, white papers, interoperability activities, and ecosystem alignment for next-generation interconnect technologies.  Track and influence scale-up, scale-out, scale-across, Ethernet/RDMA, PCIe/CXL, UCIe and other die-to-die or accelerator interconnect technologies.  Analyze interconnect protocol stacks from SerDes and PHY through link and upper-layer protocol logic, including trade-offs in bandwidth, latency, power, reach, reliability, scalability, and cost.  Evaluate copper and optical connectivity options, including board and backplane channels, copper cables, optical modules, CPO, NPO, silicon photonics, and optical I/O.  Engage with hyperscalers, cloud providers, telecom operators, semiconductor and system vendors, research institutes, and industry organizations to align technical directions and identify collaboration opportunities.  Work with internal architecture, engineering, product, standards, business development, and government affairs teams to develop company positions and provide technical recommendations.

BS/MS in Electrical Engineering, Computer Engineering, Computer Science, Communications Engineering, Microelectronics, or a related field.  8+ years of relevant experience in data center networking, high-speed interconnects, SerDes, networking or switch silicon, AI infrastructure, chiplet technologies, or system architecture.  Strong understanding of high-speed interconnects across PHY, link, and protocol layers, with hands-on knowledge in at least one core area such as SerDes, Ethernet/RDMA,  PCIe/CXL, UALink/OISA/CLink/NVLink/UB, UCIe etc.  Understanding of copper and optical transmission media, channel characteristics, and deployment trade-offs.  Working knowledge of servers, racks, supernodes, AI clusters, and the communication requirements of large-model training and inference.  Basic understanding of AI operators, collective communications, software stacks, and hardware/software development workflows.  Experience with standard organizations, industry alliances, or cross-company technical collaboration.  Strong technical writing, presentation, stakeholder management, and communication skills in both Mandarin and English.

Knowledge of advanced packaging, including 2.5D integration, 3D stacking, silicon interposers, hybrid bonding, and HBM integration.  Familiarity with CPO, NPO, silicon photonics, optical I/O, optical modules, and related thermal, power, reliability, and serviceability considerations.  Established relationships with key participants in China’s data center ecosystem, including hyperscalers, cloud providers, telecom operators, research institutes, and standards or industry organizations.  Proven ability to drive cross-company technical alignment, interoperability initiatives, and ecosystem collaboration.  Minimum Qualifications: •    Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. OR Master's degree in