R&D Engineering, Sr Engineer

Descriptions & Requirements

Job Description and Requirements

Alternate Job Titles Standard Cell Library Characterization Engineer We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent enough time in library characterization to know that a Liberty model is only as good as the corner cases you tested and the correlations you actually validated. You understand that when a designer's STA run fails because of a timing model mismatch, it is not just a data issue, it is hours of someone's schedule gone, and you take that seriously. You are comfortable moving between SPICE simulations, Liberty file generation, and debugging why a CCS noise model behaves differently than expected across PVT corners. When a correlation gap shows up between characterization and static timing analysis, you do not just log it, you dig in, reproduce it, and figure out what assumption broke down. You know the difference between running a characterization flow and owning it. Running it means you execute scripts. Owning it means you catch the issue before QA does, you spot the pattern in regression failures, and you know when a model needs another pass even if it technically meets spec. At Synopsys, you will work on standard cell libraries that power advanced node designs across the semiconductor industry. The libraries you characterize will be used in real tapeouts, and the quality bar is not negotiable.

Characterize and model standard cell libraries for advanced technology nodes, generating Liberty files including NLDM, NLPM, CCS timing, CCS noise, ECSM, LVF, AOCV, POCV, spatial OCV, aging, and EM models Handle characterization across a wide range of cell types: combinational, sequential, clock gating, synchronizers, retention, level shifters, power gating, always-on, filler, and decap cells Debug and resolve correlation issues between characterization results, static timing analysis, and SPICE simulations, working across tool flows to identify root causes Execute QA checks, regression analysis, and release validation to ensure library deliverables meet quality and accuracy standards before they ship Drive methodology improvements and automation initiatives that make characterization flows faster, more reliable, and easier to maintain across multiple projects Coordinate project execution timelines, manage deliverables, and communicate status across cross-functional teams including design, verification, and product engineering Support library releases by validating models against design rule checks, performing sanity testing, and ensuring documentation is complete and accurate The Impact You Will Have Enable accurate timing closure for advanced node designs by delivering high-quality Liberty models that designers and STA tools depend on Reduce correlation gaps between characterization and silicon behavior, improving predictability and reducing costly respins for customers Accelerate library development cycles by building automation and improving characterization flows that scale across multiple technology nodes Increase library quality and reliability through rigorous QA, regression testing, and validation processes that catch issues before release Support successful tapeouts by ensuring standard cell libraries meet performance, power, and area targets across all operating conditions Contribute to methodology evolution by identifying gaps, proposing solutions, and implementing improvements that benefit the entire characterization team Help Synopsys maintain its leadership in library IP by delivering models that meet the precision and