Layout Design , Sr Staff Engineer

Descriptions & Requirements

Job Description and Requirements

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of layout design, working at nodes where every micron matters and where a floorplan decision made in week one determines whether your PHY meets timing, power, and area targets six months later. You know the difference between a layout that passes DRC and one that actually survives EMIR, latch-up, and real-world ESD events, and you have debugged enough tapeout issues to spot trouble before it becomes a showstopper. Leading a team does not mean delegating and disappearing. You stay technical. You jump into Calibre when someone is stuck on a PERC violation at 3nm. You review floorplans with the same rigor you expect from your team. Mentoring junior engineers is not a checkbox activity for you, it is how you scale your impact, and you know how to push senior engineers to do their best work without micromanaging them. You think in tradeoffs. FinFET versus GAA at 5nm. Matching topology versus routing congestion. Customer pitch requirements versus your team's bandwidth. You do not wait for perfect specs, you work with what you have, clarify what is critical, and move the project forward. At Synopsys, you will lead layout development for DDR and HBM PHY IP that powers the memory subsystems in everything from data centers to AI accelerators.

Lead layout development for next generation DDR and HBM PHY IP across 7nm, 5nm, 3nm, and future nodes using FinFET and GAA process technologies Drive floorplanning, layout matching, ESD hardening, latch-up mitigation, and PERC/EMIR closure for analog and mixed-signal blocks in high-speed memory interfaces Own effort estimation, schedule planning, and execution for layout projects, coordinating across design, verification, and customer engagement teams Mentor junior layout engineers on deep submicron effects, DFM best practices, and advanced layout techniques while challenging senior engineers to deliver higher quality on tighter timelines Conduct layout reviews, manage quality checks using Calibre and internal flows, and drive LEF generation, bond-pad layout, IO frame design, and release processes Translate PHY-level customer requirements into actionable layout constraints and work directly with customers to resolve pitch, area, and integration challenges Stay hands-on, jumping into critical layout tasks when schedules tighten or technical problems require deep expertise to unblock the team The Impact You Will Have Your leadership will directly shape the performance, power, and area of memory PHY IP used in flagship SoCs across hyperscale data centers, AI training systems, and mobile platforms The floorplans and layout techniques you establish will become the foundation for future generations of DDR and HBM IP, influencing how Synopsys scales to next-node technologies Your mentorship will build a stronger, more capable layout team that can tackle increasingly complex process nodes and customer requirements with less escalation The quality and turnaround time improvements you drive will accelerate customer tapeouts and reduce costly respins, strengthening Synopsys relationships with top-tier semiconductor companies Your ability to translate ambiguous customer specs into executable layout plans will reduce integration risk and improve first-pass success rates for memory subsystems The cross-functional collaboration you foster between layout, design, and verification will break down silos and make the entire PHY development process more efficient