Senior Engineer - Physical Design

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 About this Opportunity  Join Ericsson's cutting-edge journey to shape the future of 5G networks! As a Physical Design Engineer, you'll work on pioneering digital ASIC designs vital to Ericsson's mobile network infrastructure. Our team, responsible for the final critical stage of chip design before fabrication, thrives on Lean and Agile principles, promoting close collaboration, daily progress-sharing, and continuous improvement. If you're passionate about advanced technology and ready to make a meaningful impact in telecom, this role is crafted just for you.  At Ericsson, we support your growth, offering opportunities to advance your skills while contributing to game-changing 5G/6G technologies. Here, you'll find a supportive, innovative environment focused on quality, teamwork, and career development. Join us and help shape the future of telecom!  We are hiring a Physical Design Engineer to own the physical implementation flow on high-performance, low-power SoC designs at advanced process nodes. Your primary focus will be die-level floorplanning, full-chip place-and-route, and timing-driven physical closure — while also contributing to synthesis and static timing analysis (STA) signoff as secondary responsibilities. You will work closely with RTL design, synthesis, DFT, and verification teams throughout the full design cycle from netlist hand-off to GDSII sign-off.  What you will do: 
 Floorplanning & Physical Implementation Own die-level and block-level floorplanning using Cadence Innovus or Synopsys ICC2 — defining die size, I/O ring placement, power ring topology, and macro placement strategies.  Perform early floorplan exploration to evaluate area, aspect ratio, and pin assignment trade-offs in collaboration with the architecture and package teams.  Plan and implement hierarchical design partitioning — define interface timing budgets, feedthrough corridors, and block-level pin constraints for clean top-level integration.  Coordinate macro placement with memory compilers, analog IP, and hard macros; manage blockage and halo constraints to minimize routing congestion.  Drive floorplan-driven synthesis feedback loops with the synthesis team; iterate on netlist placement to reduce post-route timing and congestion surprises.  Power Planning & Power Delivery Network (PDN)  Design and implement the on-chip power delivery network — power rings, power straps, and rail routing — to meet IR drop and electromigration (EM) targets.  Coordinate with power analysis teams on static and dynamic IR drop budgets; iterate on PDN to achieve sign-off across all power domains.  Implement and validate multi-voltage domain power structures per UPF/CPF — power switches, isolation cells, level shifters, and always-on logic placement.  Perform early power grid analysis to identify PDN weaknesses before detailed routing; collaborate with the package team on C4 bump and power delivery co-design.  Place and Route  Execute full-chip and block-level placement and routing targeting timing, congestion, and power objectives across all MMMC corners.  Drive timing-driven placement strategies — useful skew, path-specific placement constraints, and pre-CTS timing optimization to reduce hold and setup violations.  Perform clock tree synthesis (CTS) — define clock tree goals, buffer library selection, skew targets, and clock mesh/shielding strategies for high-frequency designs.  Manage routing for signal integrity — differential pairs, shielding of sensitive nets, and antenna rule compliance across all metal layers.  Perform detail routing, via optimization, and metal fill insertion to meet density DRC and sign-off requirements.  Physical Closure  Drive iterative timing closure — setup and hold — through ECO-driven placement and routing iterations in collaboration with the STA team.  Perform DRC, LVS, and ERC checks using Synopsys IC Validator or Cadence PVS; own physical verification sign-off to