Sr. Staff Engineer, Front-End Verification

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

We are looking for a Design Verification Engineer to contribute to the unit-level verification of our RISC-V CPU front end—including instruction fetch, branch prediction, and surrounding fetch control structures. As a key individual contributor within our front-end DV team, you will focus on building testbenches, generating stimulus, and developing checkers for complex microarchitectural scenarios.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

• Front-End Experience: Solid background verifying CPU front-end blocks—such as instruction fetch, branch predictors (BTB, TAGE, RAS), instruction caches/TLBs, or decode—using SystemVerilog, UVM, and C++.

• Unit-Level Focus: Hands-on experience building clean, controllable unit testbench environments with precise stimulus and checking.

• Reusable Design: Pragmatic approach to building transactors, predictors, and scoreboards that can be reused across verification levels.

• Collaborative Problem Solver: Comfortable working alongside RTL designers to trace and fix misspeculation, redirect, and edge-case fetch bugs.

What We Need

• Unit-Level Verification: Work within the front-end DV team to build and maintain UVM testbenches for instruction fetch units, branch predictors, and related sub-blocks.

• Stimulus Generation: Develop constrained-random and directed tests targeting speculation depth, misprediction/redirect flows, fetch bubbles, and cache/TLB interactions.

• C++ Integration: Help develop and maintain C++ reference models and predictors that integrate into the verification framework for cycle-accurate or transaction-level checking.

• Execution & Closure: Execute verification plans, track functional and code coverage metrics, and ensure edge cases are verified.

• RISC-V Front-End Microarchitecture: Practical experience with high-performance RISC-V fetch pipelines and prediction structures.

• Maintainable DV Infrastructure: Strategies for writing unit testbenches that remain manageable as designs evolve.

• Tooling & Workflows: Experience using both industry-standard simulators and open-source flows (e.g.,