Design Verification Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering ( SCHIE ) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantages to Microsoft and enable our customers to achieve more. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Shared and Custom IP & Silicon (SCIPS team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Design Verification Engineer to join our team.   #SCHIE #CSME #SCIPS Responsibilities The candidate for this position will be expected and able to complete the following responsibilities: Plan the verification of complex design IP interacting with the architecture and design engineers to identify verification test scenarios. Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools Develop tests using UVM or C/C++ Analyze and debug test failures with designers to deliver functionally correct design. Identify and write functional coverage for stimulus and corner cases. Close coverage to plug verification holes and meet tape out requirements. Collaborate with cross-functional teams, including Architecture, Design, Verification and FW to deliver products with key differentiators.  Engage in chip bring-up activities and write test firmware to assist other teams.  Drive innovation by enhancing validation efficiency through new methodologies and tools.  Embody Microsoft’s core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive Results, Influence for Impact, Judgement, and Diversity & Inclusion.

Required Qualifications: Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience OR equivalent experience.

Experience in executing pre-silicon verification of IPs/Sub Systems/SoCs through full cycle. Experience with the use of formal verification methods  Scripting language such as Python, Ruby or Perl.  Understanding of silicon chip and/or computer architecture  In depth knowledge of verification principles, testbenches and stimulus generation.  Background in creating and debugging IP/SoC Level tests in SV-UVM/C.  Experience in Assembly, start up code and linker scripts  Experience in developing Makefiles for software development.