ASIC Technical Leader - Product Quality & Productization (Hybrid)

The application window is expected to close on: 09/10/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . This position is a hybrid position with approximately 3 days in office in San Jose, California, United States. Meet the Team The Cisco Hardware Engineering Team develops and works with Next Generation Technology to build Cisco Hardware products keeping in mind the user experience and in accordance with IEEE standards, and industry protocols. Hardware Engineers serve a range of roles at Cisco from IP Creators and architects creating industry standards, to Solution Integrators driving multi-functional teams to go from concept to production, as well as providing expertise in Solution Verification and ensuring that our products meet Cisco and Industry quality standards. They drive innovation across the large Cisco portfolio, encompassing System/Board Design, Circuit Board Layout, Hardware Automation, Validation and Test, and Signal Integrity and Power Design. By partnering multi-functionally with system designers, diagnostics and customer escalation engineers, and external vendors, they ensure robust test methodology and timely issue mitigation. This collaborative approach bolsters product quality and delivers next-generation solutions through dedicated IP development, research, and a dedication to challenging the industry status quo to optimize cost and performance.

This position provides high-level technical leadership for the Silicon One organization, bridging the gap between advanced DFT architecture, silicon quality, and high-volume manufacturing. The role is responsible for the end-to-end product lifecycle—from RTL design and NPI through mass production—ensuring that our programmable silicon architecture maintains the highest industry standards for reliability, yield, and field performance. Responsibilities include: DFT Strategy & Implementation Direct the development and execution of robust DFT architectures (JTAG, SCAN, BIST) and integrate test modes at the top-level RTL. Guide multi-functional teams in integrating Design-for-Manufacturability (DFM) and DFT principles early in the development cycle to ensure optimal test coverage. NPI & Mass Production Leadership Orchestrate the transition of complex SoC products from development through New Product Introduction (NPI) to successful mass production. Manage program risks and provide executive-level status reporting on manufacturing health and yield optimization. Quality & Reliability Engineering Lead high-level Root Cause Analysis (RCA) initiatives, using advanced diagnostics to drive corrective and preventative actions. Supervise comprehensive product qualification, including Environmental Stress Screening (ESS), electrical characterization, and accelerated life testing. Implement advanced yield analysis, power binning, and fuse array repairs to drive DPPM to industry-leading lows. Data-Driven Process Optimization Monitor high-volume manufacturing data to identify trends, optimize process windows, and drive continuous yield improvement. Ensure adherence to global quality standards (ISO 9001) and maintain comprehensive technical documentation for all quality plans.

20+ years in Silicon DFT, Test, Quality, and Program Management; minimum of 5 years specifically within high-reliability hardware environments. Deep knowledge of the full ASIC development lifecycle, specifically within the Silicon One pipeline and advanced FinFET processes (6nm/7nm). Mastery of Synopsys suite (Design Compiler, Tetramax, Spyglass, VCS) and ATE (93K testers). Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related technical field.

Data Analytics: Validated expertise in Statistical Process Control (SPC) and diagnostic tools (JMP, Python, SQL). Leadership: Proven success in leading multidisciplinary teams, influencing