Senior/Principal Interface IP Verification Engineer (Pre-Silicon) - 18383

General Information

Job Title

Senior/Principal Interface IP Verification Engineer (Pre-Silicon) - 18383

Job ID

18383

City

Austin

State/Province

Texas

Date Posted

13-Aug-2026

Job Category

Engineering

Job Subcategory

ASIC Digital Design

Hire Type

Employee

Remote Eligible

No

Base Salary Range: $138000 - $ 208000

Descriptions & Requirements

Job Description and Requirements

We Are At Synopsys, we drive the innovations that shape the way we live and connect. Our technology powers the Era of Pervasive Intelligence, from AI infrastructure and cloud computing to autonomous systems and next-generation communications. As the leader in chip design, verification, and silicon IP, Synopsys enables the world's top semiconductor companies to accelerate innovation and bring groundbreaking products to market faster. Join us and help shape the future of technology.

We're looking for an experienced ASIC Verification Engineer who is passionate about solving complex protocol challenges and delivering world-class Interface IP solutions. In this role, you'll work on industry-leading PCIe, CXL, DDR, and Ethernet technologies that serve as foundational building blocks for AI accelerators, data centers, networking platforms, and next-generation SoCs. You'll collaborate with architects, design engineers, and verification experts to ensure the quality, performance, and reliability of technology used by leading semiconductor companies worldwide.

Own verification of complex Interface IP solutions, including PCIe, CXL, DDR, and Ethernet technologies. Architect, develop, and enhance scalable UVM-based verification environments and reusable verification IP. Define verification strategies and test plans from specification review through product release. Develop constrained-random, coverage-driven verification solutions using SystemVerilog and UVM. Drive functional coverage closure and verification signoff activities. Debug challenging RTL, protocol, and system-level issues while improving verification efficiency and automation. Partner closely with architecture, RTL, firmware, and systems teams to identify issues early and ensure robust product quality while also mentoring engineers contributing to verification methodology improvements across the organization. Why This Role Matters The Interface IP you help verify will be integrated into some of the world's most advanced semiconductor products. Your work will directly impact the performance, reliability, and success of technologies powering: AI and machine learning platforms Cloud and hyperscale data centers High-performance computing systems Networking and communication infrastructure Automotive and intelligent edge applications What You'll Bring BSEE with at least 8 to 10+ years of direct industry experience with proven experience verifying complex ASIC or SoC designs. Deep expertise with SystemVerilog and UVM methodologies. Strong protocol knowledge in one or more of the following areas: PCI Express (PCIe), Compute Express Link (CXL), DDR Memory Interfaces, Ethernet Experience developing constrained-random and coverage-driven verification environments. Strong debugging and problem-solving skills spanning RTL, verification, and protocol compliance. Experience with industry-standard simulators such as VCS, ModelSim, or similar tools. Ability to independently drive technical initiatives while collaborating across geographically distributed teams. Preferred Experience with verification IP development, assertion-based verification and formal methodologies with knowledge of modern SoC architectures and high-speed communication interfaces. What Success Looks Like Deliver robust, high-quality verification solutions for complex Interface IP products. Improve verification coverage, reusability, and execution efficiency. Influence verification methodologies and best practices across engineering teams. Drive successful product releases with exceptional quality