Next-Gen, High-Speed HBM, LPDDR Memory Controller ASIC Digital Design Engineer

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Next Generation, High-Speed, Memory and Cache Controller Design Team is looking for a Senior ASIC Design Engineers for the next generation high speed HBM/LPDDR/DDR memory controller. The front end of the DDR controller interfaces to the rest of the system such as CPU, GPU, DSP, Multimedia Processors and the engineer is expected to be responsible for enabling high speed (1Ghz+) designs in QCT products. Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. The candidate will work on architecture, design (RTL coding), and deployment of the next generation, high-speed memory systems into QCT products. You will develop or contribute to the development of architecture and design specifications and drive the micro-architecture of portions of the logic design. You will implement and deliver RTL and work with verification engineers to deliver high quality designs. You will be responsible for debugging your designs and also provide debug support when integrated into the rest of the chip. Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power Analysis are expected to be key tasks. You will make regular contributions to the overall improvement in design methodology to drive productivity and quality of results.

Bachelor's  or Masters degree in Science, Engineering, or related field. 5+ years ASIC design, RTL coding, front-end digital design experience 3+ years Hardware Architecture experience   Preferred Qualifications   3-10 years of ASIC design (RTL coding) Preferred Exposure to RTL Design Verification flows is a plus 3+ years of direct Hardware Architecture experience Bachelors degree in Electrical or Computer Engineering and at least 5+ years of experience in high speed digital design Master's degree preferred Experience with the following: LPDDR  memory and cache controller, NoC based architectures especially the front end interfacing to the CPU, DSP, and multimedia processors Exposure to HBM memory type designs On-chip tightly coupled SRAM & L3 cache controller architecture/design Experience with x86 or ARM CPU/bus architectures Ordering of memory transactions and methods to enforce proper ordering in order to conform to ISA architecture specification   Education Requirements   Required: Master's, Computer Engineering and/or Electrical Engineering Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail  disability-accomodations@qualcomm.com  or call Qualcomm's toll-free number found  here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). To all Staffing and Recruiting Agencies :   Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such