Physical Design Lead(High Speed IP's)

ADVANCE YOUR CAREER. ADVANCE THE WORLD.  At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.    Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. MTS SILICON DESIGN ENGINEER     THE ROLE AMD is looking for an experienced and highly motivated Member of Technical Staff (MTS) to join the CT Physical Design team. In this role, you will drive the physical implementation of industry-leading high-speed interface IPs including DDR, LPDDR, GDDR, PCIe, and other next-generation mixed-signal PHY solutions used across client, server, and graphics products.  As a technical leader, you will work closely with architects, circuit designers, RTL, package, power integrity, signal integrity, SoC, and methodology teams to define and implement innovative physical design solutions that achieve aggressive PPA, frequency, power, and schedule goals on advanced process nodes. The ideal candidate combines deep physical design expertise with strong leadership capabilities and a proven track record of delivering complex, high-performance IPs to production. THE PERSON You are passionate about solving complex physical design challenges in advanced semiconductor technologies. You thrive in fast-paced environments, influence technical direction beyond your immediate team, and enjoy mentoring engineers while driving innovation in implementation methodologies. You possess deep understanding of high-speed digital and mixed-signal design implementation and have successfully delivered multiple tape-outs in advanced technology nodes.

Lead physical design implementation of complex high-speed IPs such as DDR/LPDDR/GDDR PHYs, PCIe, SerDes, and related subsystems. Own end-to-end implementation activities including some or all of these domains: Floorplanning Power planning Placement Clock architecture CTS Timing closure Signal integrity closure Physical verification Tapeout signoff Drive high-frequency timing closure for challenging datapaths and clock distribution networks. Partner with architects and circuit designers to optimize PHY architectures for performance, power, and implementation efficiency. Develop and deploy innovative implementation methodologies to improve design quality, productivity, and scalability. Collaborate with cross-functional teams including Architecture, RTL, AMS, Package, SI/PI, Product Engineering, SoC, CAD, and EDA vendors. Mentor junior engineers and help grow the technical capability of the organization. Drive continuous improvement initiatives in automation, AI-assisted design methodologies, and signoff flows.

10+ years of industry experience in Physical Design for advanced semiconductor products. Proven track record delivering multiple successful tape-outs on advanced technology nodes (N3/N4/N5 or equivalent). Experience closing timing at aggressive frequencies and implementing complex clocking structures. Expertise with industry-standard EDA tools including Cadence and Synopsys implementation/signoff flows. Experience driving methodology development and automation. Demonstrated leadership across cross-functional teams and geographies. TECHNICAL SKILLS Physical Design and Signoff STA and Timing Closure Clock Architecture and CTS Floorplanning and Power Planning IR/EM Analysis Physical Verification SI/PI Analysis Low Power Design (UPF/CPF) Advanced Node Design Methodologies Tcl/Python/Scripting AI-assisted Design Flows (preferred) LEADERSHIP EXPECTATIONS Leads strategic technical initiatives across multiple IP programs. Mentors and develops engineering talent. Drives