ASIC Digital Design Manager

Descriptions & Requirements

Job Description and Requirements

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent a decade building IP that ships, not just passes verification. You know that the best microarchitecture is the one that survives contact with timing closure, power constraints, and the realities of a 5nm process node. You have been the person in the room who catches the CDC issue before it becomes a silicon respin, and you have learned that the hardest part of leading a design team is not writing the cleanest RTL, it is teaching five engineers to think three steps ahead without micromanaging their every line of code. You are equally comfortable reviewing a timing report at 9 a.m. and having a career conversation with a junior engineer at 3 p.m. You do not just manage projects, you grow people. When someone on your team hits a wall on a complex AXI bridge implementation, you know when to step in with technical guidance and when to let them work through it. You have strong opinions about what makes good SystemVerilog and you are not afraid to push back when an architecture decision does not make sense for the product or the schedule. At Synopsys, you will lead a team building Ethernet MAC and PCS controllers that power networking silicon across the industry. The work is technically hard, the team is real, and what you build will matter.

Lead a team of digital design engineers developing Ethernet MAC and PCS IP from microarchitecture specification through customer release Drive architectural and microarchitectural decisions for next-generation Ethernet controllers, translating customer requirements into robust, scalable RTL implementations in SystemVerilog Oversee design reviews, timing closure strategy, CDC/RDC sign-off, and synthesis quality across multiple concurrent IP development projects Manage resource allocation, project execution, and cross-functional collaboration with verification, physical design, and product teams to meet schedule and quality commitments Conduct technical interviews, assess candidate capabilities in RTL design and microarchitecture, and build a high-performing team through hiring and onboarding Mentor engineers on complex implementation challenges including high-speed interface design, multi-voltage domain architectures, and UPF-based low-power methodologies Own performance reviews, career development planning, and succession planning for your team while fostering a culture of technical excellence and continuous learning The Impact You Will Have Deliver Ethernet IP that powers networking products across the semiconductor industry, enabling high-speed connectivity in data centers, automotive, and AI systems Build and scale a digital design team capable of executing complex IP development projects with quality, predictability, and technical rigor Strengthen Synopsys IP portfolio by driving architectural innovation and design reuse across Ethernet MAC, PCS, and related high-speed interface technologies Reduce time-to-market for customers by ensuring IP releases meet timing, power, and area targets without late-stage surprises or silicon respins Grow the next generation of RTL design talent through mentorship, technical coaching, and hands-on leadership in real product development Influence cross-functional execution by providing clear technical direction, risk assessment, and tradeoff analysis that keeps projects on track Shape the technical culture of the Ethernet IP group by setting standards for design quality, code reviews, and engineering discipline What You'll Need