Senior Digital Design Verification Engineer GPU Hardware - Athens or Patra, Greece

Company: Qualcomm Europe, Inc., Greek Branch Office Job Area: Engineering Group, Engineering Group > GPU ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm GPU Engineer, you may architect, design, implement, verify, and/or optimize the performance and power of GPU cores. Qualcomm Engineers collaborate with cross-functional teams to meet and exceed customer needs.

We are looking for a highly motivated Senior Digital Design Verification Engineer to join our GPU Hardware Verification team in Greece. In this role, you will contribute to the verification of complex GPU and SoC hardware blocks, helping ensure functional correctness, performance, quality, and first-pass silicon success. The ideal candidate has strong hands-on experience with SystemVerilog, UVM, and structured design verification methodologies. You will work closely with architecture, RTL design, performance, software, and system teams across the complete verification lifecycle—from planning and testbench development through debug, coverage closure, and sign-off.

Own verification activities for complex GPU and SoC blocks from verification planning through sign-off. Develop reusable, scalable, and maintainable SystemVerilog/UVM testbenches, including agents, drivers, monitors, sequencers, scoreboards, reference models, and functional coverage. Create verification strategies, test plans, verification matrices, and traceability from requirements to tests and coverage. Develop directed, constrained-random, and scenario-based tests for functional, performance, stress, and error conditions. Verify interfaces and data movement using AMBA-based protocols, including AXI and AHB, as applicable to the design under test. Define and implement checkers, assertions, protocol monitors, end-to-end scoreboards, and reusable verification components. Analyze simulation failures, waveform behavior, logs, coverage results, and performance data to identify root causes. Collaborate with RTL designers to debug issues and drive fixes through closure. Track functional and code coverage, identify verification gaps, and lead coverage-closure activities. Support regression infrastructure, test triage, automation, and verification productivity improvements. Participate in design and verification reviews, provide technical guidance, and contribute to methodology improvements. Contribute to pre-silicon and, when required, post-silicon debug and issue reproduction.

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. 4+ years of experience in digital design verification for ASIC, SoC, processor, accelerator, or FPGA environments. Strong hands-on experience with SystemVerilog and the UVM framework. Good understanding of design verification methodology, including verification planning, test development, constrained-random stimulus, functional coverage, code coverage, assertions, scoreboarding, and regression management. Experience developing and debugging reusable UVM verification environments and components. Experience with C/C++, Python, Perl, Tcl, or other scripting and automation languages. Understanding of digital design fundamentals, RTL behavior, clocking, reset, FIFOs, pipelines, arbitration, and flow control. Experience with simulation, waveform debug, regression analysis, and industry-standard verification tools. Ability to understand complex specifications and translate them into practical verification scenarios. Strong analytical, debugging, communication, and teamwork skills.

Prior verification experience with CPU or GPU architectures. Prior verification experience with memory controller designs. Prior verification