Sr Staff Mixed-Signal Verification Engineer

Descriptions & Requirements

Job Description and Requirements

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the space where analog meets digital, and you know that the hardest bugs live at that boundary. You understand that mixed-signal verification is not just about running simulations, it is about building the methodology that catches the corner case three months before tapeout. You think in test plans, coverage models, and debug strategies that actually close, not just look good in a review. You are comfortable sitting with an analog designer to understand a bias circuit, then walking back to your desk to model its behavior in Verilog-A and build a UVM environment around it. You do not wait for perfect specs. You ask the right questions, build what you need, and move forward while others are still debating the approach. You have owned verification sign-off before. You know what it takes to get from "mostly working" to "ready to tape out," and you have the scars to prove it. When a simulation fails at 3am in a regression, you are the one who can read the waveform, trace it back through the analog-digital handshake, and know exactly where to look. At Synopsys, you will work on complex mixed-signal IP that powers the semiconductor industry. The problems are real, the stakes are high, and what you verify actually ships. What You'll Be Doing * Own end-to-end AMS verification strategy, test plans, coverage models, and sign-off for mixed-signal blocks and subsystems across complex IP projects * Build and maintain UVM/SystemVerilog verification environments that integrate seamlessly with Verilog-A, Verilog-AMS behavioral models, and mixed-signal simulators * Debug complex analog-digital interface issues, simulation convergence problems, and cross-domain failures using waveform analysis and AMS-specific debug tools * Develop assertions, monitors, scoreboards, and automated verification infrastructure that catch real bugs, not just check boxes * Drive AMS simulation efficiency improvements, optimize regression flows, and reduce debug turnaround time across the verification pipeline * Collaborate daily with analog designers, digital verification engineers, modeling teams, and architecture groups to align verification approach with design intent * Mentor verification engineers on AMS methodology, review test plans and environments, and drive best practices across the team The Impact You Will Have * Your verification methodology will directly determine whether complex mixed-signal IP tapes out on schedule or slips by months * The coverage models and test scenarios you define will catch silicon bugs before they become expensive respins * Your automation and regression infrastructure will cut verification cycle time and let the team move faster without sacrificing quality * The debug frameworks you build will make it possible for junior engineers to solve problems that used to require senior intervention * Your technical leadership will shape how the team approaches AMS verification on future projects, raising the bar across the organization * The behavioral models and monitors you create will be reused across multiple IP families, multiplying your impact beyond a single project * Your collaboration with analog and digital teams will close the gaps that typically cause late-stage integration failures What You'll Need * 8+ years of hands-on experience in AMS verification, with a proven track record of owning verification sign-off for mixed-signal designs * Expert-level proficiency in SystemVerilog and UVM, with deep