Fabrication Backend Process Engineer, Quantum AI

As a fabrication backend process engineer you will play a role in the development and manufacturing of our cutting-edge quantum processor devices. You will be responsible for the die singulation process, die cleaning process, hybridization process, and device characterization modules. Your expertise will be crucial in developing robust, scalable bonding processes and die preparation processes that meet the quality standards. You will collaborate closely with cross-functional teams, including design, test, integration and frontend engineers, to optimize device performance, yield, and reliability. Additionally, you will play a key role in the qualification of equipment and processes to establish and maintain a state-of-the-art advanced packaging technique. The full potential of quantum computing will be unlocked with a large-scale computer capable of complex, error-corrected computations. Google Quantum AI's mission is to build this computer and unlock solutions to classically intractable problems. Our roadmap is focused on advancing the capabilities of quantum computing and enabling meaningful applications. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $108000 - $153000 (USD) + 15% bonus target + equity + benefits Learn more about benefits at Google .

Partner closely with other teams (e.g., design, test, frontend, packaging) to integrate new backend modules into devices, develop and refine device probing, packaging, and measurement methodologies, and ensure successful product delivery and customer satisfaction. Lead the sustainment and development of die singulation, die preparation, device hybridization modules and device characterization. Operate and maintain associated equipment to ensure optimal process outcomes and provide rapid, expert troubleshooting of process and equipment issues to minimize downtime and maintain production goals.  Design, build, and maintain backend process infrastructure to enhance efficiency, organization, and scalability. Implement standardized work practices and optimize workflows for streamlined operations. Analyze process data to identify trends, improve stability, and drive continuous yield improvement.

Minimum qualifications: Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, or a specialized field (e.g., Optics, Sensors, Audio/DSP, etc.), or equivalent practical experience. 1 year of experience in a wafer level or die level cleanroom environment. 1 year of experience with one or more of the following: SPC (statistical process control), Electrical test (Probing), Metrologies (SEM, XPS, Interferometry), or Failure analysis. 1 year of experience in hybridization techniques, including flip chip bonding, die handling and post bonding measurement. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering, Physics, or a related field (e.g., Optics, Sensors, Audio/DSP). Experience with developing novel bump materials, scaling up die sizes, flip-chip bonding or designing robust structural bonding solutions. Experience with characterization techniques including SEM, XPS, confocal microscopy, and interferometry. Experience with statistical process control and failure analysis activities. Experience with data analysis and visualization tools such as JMP, Python, or SQL.