Staff Digital Verification Engineer GPU Hardware Design - Athens or Patra, Greece

Company: Qualcomm Europe, Inc., Greek Branch Office Job Area: Engineering Group, Engineering Group > GPU ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm GPU Engineer, you may architect, design, implement, verify, and/or optimize the performance and power of GPU cores. Qualcomm Engineers collaborate with cross-functional teams to meet and exceed customer needs. We are seeking an experienced and technically influential Staff Digital Verification Engineer to join our GPU Hardware Design team. In this role, you will lead verification strategy and execution for complex GPU and SoC hardware, working across architecture, design, RTL, emulation, software, and silicon teams. The successful candidate will combine deep hands-on expertise in SystemVerilog, UVM, and modern digital verification methodology with strong ownership, technical leadership, and the ability to drive verification quality across projects.

Own and drive the verification strategy for complex GPU, CPU, SoC, or other high-performance hardware blocks from planning through sign-off. Define verification plans, test strategies, milestones, quality criteria, and measurable coverage goals in collaboration with architecture and design teams. Architect, develop, and maintain scalable SystemVerilog/UVM environments, including agents, drivers, monitors, scoreboards, predictors, reference models, and functional coverage. Lead constrained-random, directed, assertion-based, formal-assisted, emulation, and post-silicon verification activities as appropriate. Develop verification methodologies that provide effective checking of control logic, datapaths, pipelines, interfaces, memory transactions, and corner-case behavior. Drive debug of complex failures across simulation, regressions, emulation, and silicon, identifying root causes and coordinating corrective actions. Establish coverage closure strategies and review functional, code, assertion, and scenario coverage to ensure verification completeness. Mentor verification engineers, conduct design and code reviews, and raise the technical capability of the broader DV team. Influence architecture and microarchitecture by identifying verification risks, improving observability, and recommending design-for-verification features. Collaborate with RTL, architecture, performance, power, physical design, software, and system teams to resolve issues and deliver high-quality hardware. Contribute to verification infrastructure, regression automation, reusable VIP, checkers, methodologies, and productivity improvements. Represent the verification team in technical reviews and provide clear status, risk, and sign-off recommendations to project leadership.

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. Typically 8+ years of relevant experience in digital design verification, with demonstrated technical leadership on complex projects. Deep hands-on experience with SystemVerilog and UVM-based verification environments. Strong understanding of digital verification methodology, including verification planning, constrained-random testing, assertions, scoreboards, reference models, coverage, regression, and debug. Proven experience owning verification of complex IP, subsystems, or SoC components through coverage closure and sign-off. Strong knowledge of verification planning and metric-driven verification processes. Experience with protocol verification and transaction-level checking; knowledge of AMBA protocols such as AXI and AHB is highly desirable. Experience developing reference models in C/C++, Python, or another high-level language. Experience with simulators, waveform/debug tools, regression systems, and common