SIC Physical Design, Manager

Descriptions & Requirements

Job Description and Requirements

Alternate Job Titles Physical Design Lead ASIC Physical Design Manager Backend Design Manager Place and Route Manager Physical Implementation Manager We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent a decade in physical design, and you know that the difference between a chip that tapes out clean and one that burns months in respins is usually a decision made during floorplanning that nobody questioned hard enough. You are the person who questions it. You have closed timing on designs running north of 2 GHz, and you understand that at those frequencies, every picosecond matters and every SI issue that looks small in simulation becomes a showstopper in silicon. Managing a team is not about delegation for you. It is about building engineers who can see three steps ahead, who understand why a clock tree decision today affects yield six months from now. You are comfortable in the gap between what the spec says and what will actually work. When a design review surfaces a conflict between performance targets and physical constraints, you pull the right people together, sketch the tradeoffs, and drive to a decision the team can execute against. You know the Synopsys toolchain deeply because you have lived in it. ICC2, Fusion Compiler, PrimeTime , these are instruments you have tuned to deliver results on 7nm, 5nm, and 3nm nodes where the margin for error is measured in atoms. At Synopsys, you will lead physical design for the interconnect technology that makes AI infrastructure possible.

Lead the complete physical design flow for high-speed die-to-die interconnect chips operating at 2 GHz and above, from RTL handoff through tape-out Drive floorplanning , power planning, clock tree synthesis, place-and-route, and physical verification on advanced nodes including 7nm, 5nm, and 3nm Own timing closure across all corners and modes, working with front-end teams to resolve critical paths and ensure SI/PI integrity Build, manage, and mentor a global physical design team, setting technical direction and developing engineers at multiple levels Collaborate with architecture, design, verification, and package teams to align physical implementation with product requirements and manage milestones Champion automation and methodology improvements using Tcl , Python, and Perl scripts that increase team productivity and design quality The Impact You Will Have Deliver the physical implementation for high-bandwidth, ultra-low latency chip-to-chip communication that powers AI training and inference infrastructure Set the standard for advanced-node physical design quality and methodology across Synopsys silicon engineering Drive multiple successful tape-outs on cutting-edge process nodes, ensuring first-pass silicon success Shape the physical design tool flows, automation frameworks, and best practices adopted across the organization Grow a team of engineers who become the next generation of technical leaders in physical design Advance Synopsys' position as a leader in AI silicon innovation through interconnect technology that enables next-generation systems What You'll Need 10+ years of hands-on experience in physical design with deep expertise in high-frequency chip implementation and timing closure Proven track record leading physical design on advanced process nodes including 7nm, 5nm, or 3nm with multiple successful tape-outs Expert-level proficiency with Synopsys physical design tools including ICC2, Fusion Compiler, PrimeTime , StarRC , and RedHawk Strong scripting