ASIC Design Verification Eng II Full Time - United States

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Applications accepted until further notice. Meet the Team   The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

As an ASIC Engineer, you will play a critical role in developing Cisco’s revolutionary data center solutions. You will collaborate closely with verification engineers, designers, hardware, and othercross -functional teams to verify the ASIC in simulation, in emulation, and during ASIC bring-up to help guarantee seamless integration and optimal performance of Cisco’s hardware platforms. You will:   Maintaining existing DV environments and enhancing them   Construct test bench including scoreboard, agents, sequencers, and monitors for new blocks   Write test plan, develop test cases, debug regression failures and drive to module verification closure   Ensuring complete verification coverage through implementation and review of code and functional coverage.

Meet one of the following (completed within the past 3 years or ex pected to be completed within the next 12 months):    -A Master's degree with 0 years of work experience;    -A Bachelor's degree with 2 years of work experience.    Qualifying education and work experience should be in ASIC Engineering, Verification or a related field.    Experience with System Verilog and UVM methodology .   Experience with scripting using Perl and/or Python.

Experience using UVM and SystemVerilog for ASIC verification and verifying complex blocks and/or clusters within ASICs.   Experience with functional coverage and constrained random DV environments.   Experience in verifying complex blocks, clusters and top level for SoC.   Experience with Veloce/HAPS.   Experience building test benches from scratch, including experience in SystemVerilog constraints, structures, and classes.   Effective verbal and written communication skills.   Why Cisco?  At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.  We are Cisco, and our power starts with you.  Message to applicants applying to work in the U.S. and/or Canada: Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your