Senior Staff Product Application Engineer-Memory Subsystems

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Join our team to drive customer success on the memory subsystem across our silicon portfolio, covering DDR and LPDDR across generations and the memory controller, Network-on-Chip and physical interface behind them. You will be a technical point of contact for escalated memory cases, from early design-in and bring-up through production support. You are the person strategic customers escalate to when memory does not behave the way the specification says it should. You will root-cause those failures on real systems, drive the fix through the teams that own it, and review next-generation memory architecture and design to catch defects before they reach silicon. You will also own the memory documentation customers design against. The scope runs from JEDEC device behavior and PCB routing, through controller architecture and RAS features, to the product and roadmap decisions your findings should drive. THE PERSON You have a passion for memory technology, system architecture, and hardware debug at the level where silicon, firmware, board and DRAM device all interact. You are a thorough memory expert who knows what the specification says, what the silicon actually does, and where the two diverge. You are a team player with excellent written and verbal communication skills and experience collaborating with engineers located in different sites and timezones, and you can hold a technical conversation directly with a customer. You are effective across organizations you do not manage, and you are drawn to problems that arrive without a clear owner or a clear root cause. We place a high value on technical writing. You produce documentation a customer can design against with confidence, and you can present a complex technical finding clearly to both engineering and customer audiences.

Customer Support and Debug:  Own escalated customer support issues for memory, from early design-in and bring-up through production support. Partner with key customers to root-cause system memory failures such as intermittent errors, calibration and training failures, and margin and boot issues. Attribute each correctly across DRAM, board, controller IP, calibration firmware and silicon, and drive the fix to closure. Memory Subsystem and Interconnect Expertise:  Be the authority on DDR and LPDDR, covering JEDEC standards, device behavior, module topologies, ranks, widths and supported data rates. Know how traffic reaches the controller across the Network-on-Chip, including QoS, arbitration, and bandwidth and latency budgeting. Customer Documentation and Communication:  Author the customer-facing memory documentation, including product guides, user guides, datasheets, answer records, tutorials and layout guidance, and publish resolutions internally and externally. Architecture Review and RAS Validation:  Review memory and NoC architecture and design specifications for next-generation silicon, identifying gaps, inconsistencies and design bugs, and proposing fixes. Evaluate and validate its memory RAS features. Signal and Power Integrity:  Perform DRAM SI/PI and timing measurements. Apply PCB layout and routing knowledge for DDR and LPDDR to assess customer designs and define the layout guidance we publish. Support IBIS/IBIS-AMI models and channel simulation. Memory Health Tooling and Experiments:  Create experiments and tooling that catch memory health issues before