Design Verification Engineer — Memory Subsystem

Company: Qualcomm Canada ULC Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Qualcomm is seeking a motivated and experienced Design Verification Engineer to join its memory subsystem verification team. The successful candidate will be responsible for developing and executing comprehensive verification strategies for complex digital designs, including memory controllers, DDR/LPDDR/HBM and custom memory interfaces, PHY-related logic, and other high-performance memory subsystem components. This role involves the complete verification lifecycle—from understanding design specifications and developing verification plans to creating UVM-based testbenches, developing assertions, executing simulations, debugging failures, and driving functional and code coverage closure. The ideal candidate will have strong hands-on experience with Verilog, SystemVerilog, UVM, and SystemVerilog Assertions, along with an interest in memory technologies such as LPDDR, DDR, HBM, and JEDEC specifications.

Develop verification strategies, test plans, and coverage plans for complex RTL designs. Build, enhance, and maintain reusable SystemVerilog/UVM and formal verification environments. Develop and maintain UVM components, including: Sequences and sequence libraries Drivers and monitors Scoreboards and reference models Agents, environments, and test configurations Functional coverage models Create and execute constrained-random, directed, error-injection, and corner-case tests. Write and maintain SystemVerilog Assertions for protocol, interface, timing, and functional verification. Verify memory-controller, PHY-interface, and memory-subsystem functionality across multiple operating modes. Analyze simulation failures using waveform viewers, simulation logs, transaction databases, and other debug tools. Perform root-cause analysis of verification failures and collaborate with RTL, architecture, modeling, and integration teams to resolve issues. Review RTL, microarchitecture specifications, interface definitions, and design changes for functional correctness, completeness, and verifiability. Support regression execution, failure triage, failure classification, and verification status reporting. Drive functional, code, assertion, and coverage closure. Collaborate with cross-functional teams, including architecture, design, physical design, firmware, modeling, and system validation teams.

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. 3–10 years of experience in ASIC, SoC, IP, or subsystem design verification. Strong hands-on experience with: Verilog SystemVerilog UVM SystemVerilog Assertions Experience developing and debugging reusable UVM-based verification environments. Proficiency in developing UVM components such as sequences, drivers, monitors, scoreboards, agents, and functional coverage models. Experience with constrained-random verification and coverage-driven verification methodologies. Experience writing assertions for protocol compliance, temporal behavior, interface checking, and functional correctness. Strong understanding of digital design and verification fundamentals, including clocking, reset behavior, synchronous and asynchronous logic, and multi-clock-domain designs. Experience with simulation-based verification, waveform analysis, regression execution, and failure debug. Strong analytical, problem-solving, communication, and collaboration skills.

Experience verifying LPDDR, DDR, DDR PHY, HBM, custom memory interfaces. Familiarity with JEDEC memory specifications and memory-protocol requirements. Understanding of memory-controller, memory-subsystem, and PHY architecture. Familiarity with integrating and configuring industry-standard verification IP. Experience working with commercial or internally developed memory models. Experience with power-aware