ASIC Digital Design Engineer, Staff -Sr Staff

Descriptions & Requirements

Job Description and Requirements

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You are a digital design engineer who takes pride in delivering RTL that is not only functionally correct, but also clean, synthesizable, and ready for real silicon. You enjoy working through the details—timing, CDC, lint, and design quality—because you know they matter when IP ships in customer products. You work well in a collaborative, global environment. You communicate openly with design, verification, and implementation teammates, ask thoughtful questions when specs are unclear, and are willing to learn new tools and methodologies, including AI-driven design approaches. Whether you are deepening your expertise or guiding others through complex challenges, you bring ownership, curiosity, and a practical mindset to your work.

Understand industry standards and functional specifications, and contribute to architecture and micro-architecture definitions for complex protocol IP cores Design and implement RTL for digital blocks and subsystems in Verilog/SystemVerilog, balancing performance, area, power, synthesizability, and testability Perform basic verification and collaborate with verification teams on test planning, assertion development, functional debug, and coverage closure Perform RTL-level timing analysis during RTL development, and collaborate with implementation teams on STA, timing constraints, and synthesis as needed Support CDC/RDC/Lint signoff readiness and collaborate on design-quality closure Apply and explore AI-driven design tools and methodologies to improve design quality and automation The Impact You Will Have Your RTL will directly influence the quality and time-to-market of Synopsys IP used by semiconductor companies worldwide You will reduce iteration cycles between front-end and back-end teams by delivering synthesis-ready, timing-aware designs Your collaboration will catch issues earlier, reducing costly respins and late-stage fixes The automation you build will improve design productivity for your team and beyond Your attention to CDC/RDC/Lint readiness will strengthen product quality and reduce signoff risk What You'll Need Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field 4~15+ years of experience in digital design and/or RTL development Hands-on experience designing and implementing synthesizable RTL in Verilog/SystemVerilog, with understanding of performance, area, power, and testability tradeoffs Experience with test planning, assertion development, basic verification, functional debug, and coverage closure Experience performing RTL-level timing analysis, with practical understanding of STA, timing constraints, and synthesis Experience with CDC/RDC/Lint signoff-ready design practices and design-quality closure Scripting experience in Python, Tcl, Perl, or Shell Written and oral communication skills in English and Japanese, with the ability to collaborate effectively across teams Nice to Have Direct experience with PCIe or CXL IP design and development Experience with low-power design and power intent development using UPF Exposure to UVM or formal verification concepts Exposure to functional safety concepts, ISO 26262, or FMEDA Experience mentoring engineers or serving as a technical lead on RTL/IP development projects Prior experience in a global product engineering environment Who You Are You take ownership of your work and follow through on issues until they are properly resolved You collaborate openly across teams and