SoC Physical Verification Engineer, HBM

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for  all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Physical Verification Engineer, you will be a key technical contributor within the Heterogeneous Integration Group (HIG), responsible for defining, executing, and driving sign-off quality physical verification flows for next‑generation HBM logic die and memory‑centric SoCs. You will work across physical design, design rule development, EDA tool teams, foundry interfaces, and product engineering teams to deliver industry‑leading, tape-out-ready silicon under aggressive schedule, quality, and reliability constraints. This role combines full-chip physical verification ownership — including DRC, LVS, ERC, and DFM — with deep collaboration across implementation and silicon bring‑up, ensuring design integrity from layout through first silicon. Responsibilities will include, but are not limited to: Implement physical verification sign‑off for full‑chip and hierarchical designs, including Design Rule Check (DRC), Layout Versus Schematic (LVS), Electrical Rule Check (ERC), Physical Electrical Rule Check (PERC), antenna checking, and Design for Manufacturability (DFM). Implement and debug foundry‑qualified rule decks, manage waivers, and drive clean closure while ensuring compliance with advanced‑node foundry requirements. Perform reliability verification across multiple power domains, including electrostatic discharge (ESD), latch‑up, electromigration, floating nets, and connectivity checks. Run density, metal fill, and chemical mechanical polishing (CMP) checks to ensure yield‑aware manufacturability at 3 nanometer and below. Perform parasitic resistance‑capacitance (RC) extraction and support correlation of physical verification results with post‑silicon measurements. Develop, maintain, and optimize physical verification flows, automation, and regression infrastructure using Python, Tcl, Perl, or similar scripting languages. Drive adoption of machine learning (ML) and artificial intelligence (AI)‑based physical verification and power‑performance‑area (PPA) optimization tools. Partner with physical design, custom layout, computer‑aided design (CAD), register‑transfer level (RTL), product engineering, EDA, and foundry teams, including direct collaborate with TSMC, from design kick‑off through tape‑out readiness and sign‑off decision gates. Demonstrating AI to develop AI assisted development workflows.

Experience with full‑chip or block‑level physical verification for advanced‑node system‑on‑chip, memory, or heterogeneous integration designs. Experience in physical verification methodologies, including DRC, LVS, ERC, PERC, DFM, antenna, and reliability sign‑off. Experience using industry physical verification tools such as Calibre, IC Validator (ICV), Pegasus, or similar, including rule deck development or customization. Working knowledge of full RTL‑to‑GDS implementation flows, including place‑and‑route, extraction, and their impact on physical verification outcomes. Ability to drive verification closure by maintaining strong communication with multi-functional teams in a global engineering environment. Proficiency with demonstrating AI and AI-enabled development workflows.

Experience with high‑bandwidth memory (HBM), DRAM, or memory‑centric system‑on‑chip physical verification, including multi‑die, chiplet, or