Advanced Power Integrity & Power Delivery Architect

About Rivian Rivian is on a mission to keep the world adventurous forever. This goes for the emissions-free Electric Adventure Vehicles we build, and the curious, courageous souls we seek to attract. As a company, we constantly challenge what’s possible, never simply accepting what has always been done. We reframe old problems, seek new solutions and operate comfortably in areas that are unknown. Our backgrounds are diverse, but our team shares a love of the outdoors and a desire to protect it for future generations.

Summary We are seeking a highly skilled and motivated Power Integrity & Power Architecture Engineer to lead the end-to-end design, modeling, simulation, and post-silicon validation of advanced SoC power delivery architectures. In this role, you will bridge the gap between System-on-Chip (SoC) design, power architecture, silicon packaging, and system-level power integrity Responsibilities Power delivery architecture, Design & Simulation ● Power Delivery Network (PDN) & Architecture: Define and optimize overall SoC power architecture, establishing target impedance, transient droop specifications, and efficiency targets across the full path: SoC/Packaging/Board. ● Advanced Power Supplier Architecture: Define requirements and simulation flows for next-generation power supplier architectures, such as IVRs, integrated switching regulators. Co-optimize power delivery for high efficiency, low supply ripple, tight transient droop targets, and strict thermal limits across the SoC, package and system. ● SoC Integration: Perform co-design and co-optimization for silicon packaging, interposers, embedded passives to ensure robust power integrity. ● Multi-Domain Modeling: Conduct pre- and post-layout power integrity (PI), signal integrity (SI), and IR/droop simulations using industry-standard 2.5D/3D field solvers and circuit simulators. Power integrity Validation ● Post-Silicon Bring-up & Correlation: Lead post-silicon validation and silicon power integrity measurements (micro-probing, high-frequency VNAs, transient load steppers, real-time scope measurements for PDN noise) to correlate lab data with pre-silicon simulation models. ● System & Platform Validation: Collaborate with hardware and SoC bring-up teams to validate SoC platforms under real-world dynamic workloads, verifying transient performance, decoupling strategies, and power delivery margins. Methodology ● Automation & Flow Optimization: Work alongside CAD and tool teams to automate power integrity analysis, extraction workflows, and simulation scripts (Python, Tcl, SKILL). Qualifications ● Education: Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. ● Experience: Proven industry experience in Power Integrity (PI), Power Architecture for SoCs and advanced 2.5D/3D/MCM packaging. ● SoC Packaging: Deep understanding of System-on-Chip (SoC) power distribution, package stack-ups, bump/ball maps, and silicon-package interactions. ● Simulation & Tool Expertise: ○ EM & Extraction: Ansys HFSS, SIwave, Cadence Sigrity/Voltus-Fi, or Keysight ADS. ○ Circuit & PDN Simulation: HSPICE, Spectre, ADS, or SIMPLIS/SIMetrix. ● Post-Silicon Validation Capabilities: Hands-on expertise with high-speed lab equipment (VNAs, oscilloscopes, active probes, impedance analyzers, load steppers) for physical power validation and PDN characterization. ● Fundamentals: Strong foundation in power architecture, electromagnetics, transmission line theory, s-parameters, and power distribution network (PDN) noise dynamics. Preferred Skills: ● Automation & Scripting: Proficiency in Python, Tcl, Perl, or Cadence SKILL for automating simulation and extraction pipelines. ● Behavioral Modeling: Experience with Verilog-A, AMS, or SystemC for macro-level system power modeling. ● Interface Noise Co-Design: Familiarity with high-speed interfaces (e.g., PCIe, DDR, UCIe, die-to-die interconnects) and mitigating power