ASIC Front-End Methodology Engineer

ADVANCE YOUR CAREER. ADVANCE THE WORLD.  At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.    Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.   ASIC Front-End Methodology Engineer THE ROLE: The Front-End Methodology Engineer (FlowCzar) will be responsible for driving consistency, scalability, and quality across ASIC front-end implementation flows spanning multiple chiplets, subsystems, and SoCs. This role owns methodology governance, tool deployment, version management, ruleset alignment, and flow consistency across projects to ensure predictable execution and high-quality deliverables.   The engineer will work closely with Design, CAD, Physical Design, Verification, DFT, and Program teams to standardize best practices and enable seamless adoption of front-end methodologies across the organization. Success in this role requires strong technical expertise, exceptional communication skills, and the ability to influence and coordinate across multiple teams and stakeholders, including customer-facing engagements.

Own and drive front-end methodology alignment across multiple chiplets, subsystems, and SoC programs. Manage tool qualification, deployment, version control, and migration strategies across projects. Develop, maintain, and govern front-end flow infrastructure, methodology guidelines, and design rulesets. Partner with CAD teams to evaluate, deploy, and support new methodologies, EDA tools, and automation solutions. Coordinate with Design, Physical Design, DFT, Verification, and Architecture teams to ensure methodology requirements are understood and implemented consistently. Identify flow gaps, integration issues, and methodology risks early, and drive closure plans across stakeholders. Define and track methodology compliance metrics, quality indicators, and readiness criteria. Drive root-cause analysis for flow-related issues and implement long-term solutions to improve execution efficiency and quality. Lead cross-functional technical reviews, alignment meetings, and customer-facing discussions related to methodology, flow readiness, and tool deployment. Mentor engineers and provide technical leadership for methodology adoption and best practices.

Strong experience in ASIC front-end implementation methodologies and EDA tool flows. Experience managing tool versions, methodology releases, rulesets, and multi-project flow deployments. Understanding of RTL-to-GDS implementation flows, including synthesis, constraints, CDC, lint, DFT, STA, and physical design interactions. Experience working across multiple IPs, subsystems, chiplets, or SoC programs with methodology governance responsibilities. Experience developing automation, scripting, dashboards, or AI-enabled solutions for flow management and quality improvement. Strong debugging and problem-solving skills with the ability to drive issue resolution across organizational boundaries. Familiarity with configuration management systems, regression infrastructure, release processes, and tool qualification methodologies. Experience defining methodology standards, signoff requirements, and best practices for large-scale ASIC programs. Excellent written, verbal, presentation, and customer-facing communication skills. Ability to influence stakeholders and drive alignment across geographically distributed teams. ACADEMIC CREDENTIALS: Bachelor's degree with 8+ years of experience, or Master's degree with 6+ years of experience, in Electrical Engineering, Computer Engineering, Computer Science, or a related field.