Senior Design Verification Engineer

Senior Design Verification Engineer    This role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office.

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.

We are seeking a talented and driven   Senior Design Verification Engineer   with specialized knowledge   and experience   in   emulation - based verification   to join our engineering team. In this role, you will be responsible for developing and executing comprehensive verification strategies for complex digital designs, ensuring functional correctness and performance targets are met prior to silicon tape-out. You will work closely with design, architecture, and validation teams to define verification plans, build robust testbench environments, and drive coverage to closure. A key focus of this position is leveraging emulation-based platforms to accelerate system-level verification, enabling early software bring-up and full-chip validation at scale. This is an excellent opportunity for a verification professional looking to deepen their expertise in cutting-edge verification methodologies and emulation technologies.

Develop and execute verification plans for IP-level and system-level designs.   Build, maintain, and enhance UVM/ SystemVerilog -based testbench environments including scoreboards, monitors, drivers, and coverage models.   Develop and run directed and constrained-random test cases to achieve functional and code coverage goals.   Set up, configure, and run designs on emulation platforms (e.g., Cadence Palladium, Synopsys   ZeBu , Mentor Veloce) for system-level verification and performance validation.   Collaborate with design teams to define verification strategies, review specifications, and identify corner cases and potential design risks.   Debug complex design issues using waveform analysis, log analysis, and emulation platform debug tools.   Develop and maintain assertion-based verification (SVA) to complement simulation and emulation efforts.   Drive coverage closure and generate verification sign-off reports.   Support software and firmware teams with early bring-up activities on emulation platforms.   Continuously improve verification processes, flows, and infrastructure.   ​ Minimum Qualifications   Bachelor's degree   in Electrical Engineering , Computer Engineering, or Computer Science.   5 – 8 years   of professional experience in design verification of digital/mixed-signal designs.   Strong proficiency in   SystemVerilog   and   UVM   methodology.   Hands-on experience with   emulation-based verification platforms   (e.g., Cadence Palladium, Synopsys   ZeBu , or Mentor Veloce).   Solid understanding of digital design concepts including RTL design, synthesis constraints, and timing.   Experience with constrained-random verification, functional coverage, and code coverage-driven methodologies.   Proficiency in debugging complex hardware designs using simulation and emulation tools.   Familiarity with scripting languages such as   Python ,   Perl , or   TCL   for automation and flow development.   Strong analytical and problem-solving skills with excellent attention to detail.   ​ Preferred Qualifications   Master's degree   in Electrical Engineering ,