Staff CPU Physical Design Engineer

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits Learn more about benefits at Google .

Lead end-to-end physical design strategy and execution for top-level and critical CPU blocks across advanced process nodes. Pioneer novel physical design methodologies, tool flows, and AI/ML optimization techniques to maximize power, performance, and area (PPA). Resolve complex timing, power grid, electromigration and IR drop (EMIR), and physical verification bottlenecks in tight iteration loops. Drive technical roadmaps, mentor executive engineering peers, and influence architectural trade-offs across cross-functional teams.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10 years of experience in high-performance, low-power physical design implementation or design convergence techniques with custom or industry standard synthesis, PnR and signoff tools. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience leading cross-functional engineering initiatives across Architecture, RTL, DFT, and Technology partners to optimize sub-system microarchitecture. Understanding of power grid design, EMIR constraints, and low-power implementation techniques. Track record of architecting CPU class physical design methodologies, custom tool enhancements, or AI/ML-assisted PPA optimization flows.