Junior SoC IP Design Engineer, Google Cloud

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Our Platforms Infrastructure Engineering team designs and builds the hardware and software technologies that power all of Google's services. Our computational challenges are complex and unique, enabled by custom hardware designed and made in-house. As a hardware engineer, you will design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You will see those systems from concepts all the way through to high-volume manufacturing. Your work has the potential to shape the machinery that goes into our data centers, affecting millions of Google users.

Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline etc. Perform RTL development (coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks. Participate in synthesis, timing/power closure and ASIC silicon bring-up. Participate in test plan and coverage analysis of the block and SOC-level verification. Communicate and work with multi-disciplined and multi-site teams.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 1 year of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. Experience with design sign off and quality tools (Lint, CDC , etc.). Preferred qualifications: Master's degree or PhD in Computer Science, or a related technical field. Knowledge in one of these areas: Peripheral Component Interconnect Express (PCIe), Universal Chiplet Interconnect Express (UCIe), Double Data Rate (DDR), Advanced eXtensible Interface (AXI), Advanced RISC Machine (ARM) processors family. Knowledge of high performance and low power design techniques. Knowledge of assertion-based formal verification. Knowledge of SOC architecture. Excellent problem-solving and debugging skills.