R&D Engineering, Staff Engineer (Design Verification/ VIP Verification Engineers)

Descriptions & Requirements

Job Description and Requirements

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years building Verification IP that engineers actually trust, not just IP that passes a checklist. You know that a VIP is only as good as the edge cases it catches and the clarity it brings when something breaks at 2 a.m. in a customer lab. Debugging a protocol violation three layers deep does not frustrate you, it pulls you in because finding the root cause matters more than closing a ticket. You think in coverage metrics and corner cases. When you read a protocol spec, you are already mapping out the sequences that will stress the implementation in ways the design team has not considered yet. You have worked with NVMe, PCIe, USB, Ethernet, or similar protocols long enough to know where the gaps usually hide and what good verification architecture looks like when it scales across products and customers. Working directly with customers during deployment does not feel like a distraction, it feels like the part where you learn what actually matters. You bring tasks to closure because leaving something half done keeps you up at night. At Synopsys, you will work with protocol experts, Design IP teams, and some of the best verification tooling in the industry, and what you build will ship into semiconductor development workflows worldwide.

Design, develop, and maintain Verification IP using SystemVerilog and UVM for industry-standard protocols including AMBA, PCIe, USB, Ethernet, UEC, UAL, and MIPI Build comprehensive verification plans that map protocol specifications to testable scenarios, coverage goals, and corner case strategies Code sequences, test scenarios, and checkers that drive coverage-based verification across functional and code coverage dimensions Debug complex simulation failures across multi-layer protocol stacks, identifying root causes in both VIP logic and customer integration environments Enhance existing VIP products for performance, reusability, and scalability as protocols evolve and customer use cases expand Support customers during VIP integration and deployment, troubleshooting issues, answering technical questions, and ensuring successful bring-up Collaborate with Design IP teams, R&D engineers, and field application teams to align VIP capabilities with product roadmaps and customer needs The Impact You Will Have Your VIP will enable faster, more reliable verification for semiconductor companies building next-generation SoCs and AI-powered products Coverage-driven verification strategies you implement will catch critical protocol violations before they reach silicon, saving months of debug time downstream Enhancements you make to existing VIP products will improve performance and expand protocol support across the Synopsys IP portfolio Customer deployments you support will directly influence how engineers at leading semiconductor companies adopt and trust Synopsys VIP Verification plans you create will set the standard for how protocol compliance is validated across complex, multi-protocol designs Collaboration with Design IP teams will tighten the feedback loop between design and verification, improving quality across both disciplines Your work will contribute to a VIP product line used globally in semiconductor development, affecting how chips are verified at scale What You'll Need Bachelor's or Master's degree in Electronics Engineering, Computer Science, or equivalent practical experience 5+ years of hands-on experience developing Verification IP Strong proficiency in