Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. NVIDIA is seeking a Senior ASIC Compose Verification Infrastructure and Tools Engineer to advance the systems that qualify, integrate, and deliver complex ASIC IP across multiple products. This role is ideal for an RTL compose or pre-silicon verification engineer who has developed a strong interest in infrastructure, automation, CI, metrics, and efficiency tooling. Our high-speed IO infrastructure team develops the flows that keep large-scale ASIC development moving: integration automation, pre-submit qualification, build and verification infrastructure, operational metrics, and debug workflows. You will work across build, verification, firmware, methodology, and infrastructure teams to make sophisticated engineering systems faster, more reliable, and easier to reason about. You’ll also have access to innovative AI efficiency tools, and we’re looking for someone excited to help us apply them effectively. What You’ll Be Doing: Apply practical AI workflows where they build leverage, including debug assistance, run triage, summarization, documentation, and workflow automation. Build and improve high-speed IO integration, build, simulation, and pre-submit qualification flows for large ASIC IP development. Improve CI reliability, turnaround time, debuggability, and scalability across distributed compute environments. Root-cause complex failures across development, verification, build systems, tools, infrastructure, and compute environments. Turn recurring integration or qualification difficulties into durable automation and process improvements. Define, publish, and actively use metrics for integration latency, flow health, failure trends, and engineering efficiency. Bring metrics into engineering discussions to guide priorities, forecast risk, and optimize the systems we operate. Collaborate with ASIC designers, verification engineers, firmware engineers, methodology teams, and infrastructure partners. Dive into unfamiliar technical areas, understand how the system works end to end, and drive ambiguous problems to closure. What We Need To See: BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience. 5+ years of relevant industry experience. Strong understanding of ASIC development workflows, including builds, simulation, regressions, debug, integration, and qualification. Experience with verification methodology such as UVM or similar. Strong working knowledge of Verilog/SystemVerilog, including RTL development or pre-silicon verification/debug experience. Exposure to industry simulation and debug tools such as VCS, Verdi, Xcelium, or similar. Strong programming skills in Python, Perl, or another scripting/systems programming language. Experience with SystemVerilog and object-oriented verification environments. Strong root-cause analysis skills, especially for intermittent or hard-to-isolate infrastructure failures. Self-directed execution: ability to take a loosely defined technical problem, investigate across domains, and deliver a working solution. Ways To Stand Out From The Crowd: Established passion for infrastructure, automation, and driving efficiency gains outside your core RTL or DV tasks. Strong curiosity about how complex systems operate and a track record of diving