Senior Staff RF/Analogue IC CAD Engineer - Farnborough, Qualcomm

Company: Qualcomm Technologies International Ltd Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: We are seeking a highly skilled and experienced Senior Staff RF/Analogue IC CAD Engineer to join our engineering team based in Farnborough, Hampshire, UK or Sophia Antipolis, France. In this role, you will be responsible for developing, maintaining, and optimizing CAD environments, design flows, and methodologies to support the delivery of world-class RF and analogue integrated circuits. As a Senior Staff engineer, you will provide technical leadership, influence cross-functional CAD strategy, and serve as a subject matter expert across the organization. The tasks will include: Design, develop, and maintain Cadence-based CAD flows for RF and analogue IC design, including schematic capture, simulation, layout, and verification. Develop and maintain SKILL/SKILL++ scripts and automation to enhance designer productivity within the Cadence Virtuoso environment. Manage and support simulation frameworks using tools such as Spectre, ADE, and Maestro, including setup of corner libraries, Monte Carlo, and process variation analyses. Own and maintain physical verification flows, including LVS, DRC, PERC, and ERC, ensuring clean sign-off at all stages of the design cycle. Collaborate with foundry partners to integrate and qualify PDK updates and new process nodes. Manage design data and CAD assets using version control systems, including Design Sync (Mentor/Siemens), ensuring integrity and traceability throughout the design lifecycle. Provide technical leadership, mentoring, and CAD support to design and layout engineers at all levels. Participate in design reviews and contribute to the overall quality of IC deliverables. Influence and shape long-term CAD strategy in collaboration with senior engineering leadership. Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Acts as a senior technical leader and key contributor in a complex, fast-paced IC design environment. Responsible for the delivery and continuous improvement of robust, scalable CAD flows and methodologies. Solves complex CAD and design flow challenges across multiple process nodes and technology generations. Fully competent in Cadence-based RF/analogue CAD environments, physical verification flows, and SKILL automation. Keeps abreast of new tool developments and industry best practices; serves as the go-to technical expert for CAD infrastructure. Ensures quality and integrity of CAD solutions; works with design and project leads to ensure timely and reliable delivery of design infrastructure.

Python scripting knowledge for automation, data analysis, and tooling within CAD and verification flows — a beneficial addition to complement the role, but not a prerequisite. Experience with regression frameworks and automated simulation/checking environments. Familiarity with backend flows including extraction, post-layout simulation, and sign-off verification. Knowledge of mixed-signal design flows and associated challenges. Exposure to EM simulation tools (e.g., Momentum, EMX, HFSS). Experience with Git or Perforce in addition to Design Sync. Good team player with strong interpersonal and communication skills. *References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and