Senior Engineer - Frontend CAD

Join our Team 
 About this opportunity: Are you a hands-on engineer and ready to shape the future of silicon verification methodology and tools on a global scale?  Join our Design Verification Methodology team — a newly established global group defining methodologies and EDA workflows across our R&D sites in Bangalore, Austin, Stockholm, and Lund.  We are part of the Ericsson Silicon engineering unit, developing state-of-the-art ASICs and FPGAs at advanced technology nodes for Ericsson’s 5G and 6G product portfolio. Our environment offers deep technical challenges, opportunities for growth, and a wealth of expertise to learn from. Last year we started a new Silicon R&D center in Bangalore, ready to join?  You will do: 
 In this high-visibility role, you will shape the next generation of  Front-End CAD (FECAD)  methodologies, DV flows, and infrastructure for ASIC IP and SoC development. Major part of your work is to work with DV activities of our proprietary tools development.  Your impact will be central in optimizing methodologies and EDA workflows, driving efficiency and innovation  across our global silicon engineering community. We are particularly interested in individuals with exposure to or interest in applying AI/ML techniques to silicon design and verification  — a significant plus as we invest in  AI-driven design automation . If you thrive on solving technical challenges, spotting opportunities for improvement, and driving continuous innovation, we’d love to have you on our team.   You will bring: 
 Deep expertise in  Testbench Architecture  using  SystemVerilog and UVM  at IP, ASIC, and/or SoC level. Previous hands-on experience in scripting (Python, Perl, bash, csh, etc.). Strong knowledge of layered UVM environments , reusable testbench components, and block/subsystem/SoC-level verification strategies. Solid understanding of directed and constrained-random verification , SVA, functional and code coverage closure. Proficiency with front-end EDA tools: Verilog simulators, RTL/verification linters, CDC checkers, and formal verification. Experience with CI methodologies and tools  (e.g., Jenkins). Strong grasp of modern silicon design methodologies  and verification best practices. Experience collaborating across geographically distributed teams . Excellent communication skills and a strong sense of ownership in solving complex infrastructure challenges. Exposure to AI/ML applications in design and verification flows  (e.g., testbench optimization, anomaly detection, coverage prediction) is a  significant advantage .   Responsibilities: 
 Lead  the development, verification, deployment, and support of complex front-end DV tools / flows. Identify and solve  flow, methodology, and tool inefficiencies across IP/ASIC/SoC environments;  productize solutions  to improve silicon quality and verification productivity. Drive innovation  in design and verification processes, including AI-based enhancements. Collaborate closely with design, verification, test, and manufacturing teams to align on methodology, quality, and timelines. Troubleshoot  technical challenges and implement scalable, long-term solutions. Foster a collaborative, forward-looking culture  within the verification community.

BS/MS  in Electrical Engineering, Computer Science, or related field. 10+ years  of relevant experience in ASIC design verification.   * 
 “All academic credentials must be from recognized and accredited institutions and are further subject to verification.” Why join Ericsson? At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the