Staff Validation/Verification Engineer - 17399

Descriptions & Requirements

Job Description and Requirements

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are We are seeking a Staff Validation Engineer to own bring-up, validation, characterization, and debug of high-speed memory PHY subsystems including DDR, LPDDR, and HBM. You will work across silicon, firmware, board, and system domains from first silicon through production readiness and help define validation strategy, lab methodology, and automation infrastructure. This is a hands-on technical leadership role for someone who is equally comfortable with oscilloscope/VNA/BERT measurements, board-level design tradeoffs, and building automation to scale validation across PVT corners and product generations.

Lead post-silicon bring-up and validation of DDR, LPDDR, and HBM PHY subsystems on evaluation boards and customer-like platforms. Execute and own PHY training/tuning validation (read/write leveling, gate training, Vref/ODT, timing alignment, calibration convergence, margining). Develop and run functional, performance, stress, corner-case, and reliability validation across voltage, temperature, and frequency. Characterize bandwidth, latency, eye/margin, jitter, BER/error rates, and subsystem stability under real workloads. Perform hands-on measurements using lab equipment including: Real-time and sampling oscilloscopes (eye diagrams, jitter, clock/data analysis) Vector Network Analyzer (VNA) for impedance, S-parameters, and channel characterization BERT (Bit Error Rate Tester) and protocol/compliance tools where applicable Power supplies, logic analyzers, thermal chambers, and related bench equipment Correlate lab measurements with silicon behavior; drive root-cause analysis from analog/signal-quality observations to firmware/silicon fixes. Support JEDEC compliance and interoperability testing for DDR/LPDDR families and HBM-related validation flows. Partner with hardware teams on EVB/validation board design, stack-up, routing, termination, power delivery, and debug access (probes, headers, rework). Provide feedback on SI/PI, connector/DRAM placement, reference designs, and design-for-validation (DFV) features. Support board bring-up, BOM review, and hardware rework/debug during validation cycles. Design and maintain Python/C-based automation for test execution, instrument control, data capture, sweeps, regression, and reporting. Improve lab efficiency through scripted instrument setups, automated pass/fail criteria, and dashboards for engineering and program reviews. Influence validation methodology, coverage metrics, and infrastructure for future silicon generations. The Impact You Will Have Your validation work directly determines whether Synopsys memory IP is ready to ship, affecting product timelines and customer confidence across the semiconductor industry The test automation you build scales across multiple IP products and releases, reducing validation cycle time and increasing coverage Your characterization reports become the technical foundation for customer engagements, sales collateral, and internal design reviews Debug rigor you bring to silicon issues prevents costly respins and field failures, protecting both schedule and reputation Test methodologies you develop and standardize become the playbook for future validation engineers joining the Nepean lab Customer issues you resolve keep high-stakes programs moving, often under tight timelines where your responsiveness is the difference between a delay and a win The data you collect and analyze feeds back into design improvements, tightening the loop