ASIC Package SI/PI Engineer

OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform.

Overview We are seeking an experienced ASIC Package Signal Integrity / Power Integrity Engineer to drive electrical architecture, modeling, optimization, and validation for the most advanced AI/HPC silicon and package design. This role focuses on high-speed SerDes and memory channel architecture, advanced 2.5D/3D package SI/PI, substrate to package co-design, power-delivery-network optimization, electromagnetic modeling, and simulation-to-measurement correlation. The ideal candidate has strong hands-on experience with high-speed channel and PDN analysis across ASIC packages, interposers, substrates, and power-delivery structures, and can translate simulation results into practical design requirements for interposers and package substrate design optimization. The engineer will work closely with ASIC, package, system, mechanical, thermal, power, and silicon validation teams from early architecture and feasibility studies through production bring-up. In this role you will Own SI/PI architecture and analysis for advanced AI ASIC packages from early feasibility studies through production. Develop and optimize high-speed electrical channels for 200G/400G SerDes, PCIe, HBM, DDR, and chiplet/die-to-die interfaces. Perform package, interposer and substrate modeling using 2D/3D electromagnetic solvers. Define and optimize package stack-ups, transmission-line structures, via transitions, breakout structures, return paths, ground shielding, bump maps, and ball maps based on SI/PI requirements. Develop channel loss, crosstalk, impedance, skew, return-loss, and link-budget requirements, and translate them into actionable package layout guidelines. Perform package-level PDN analysis, including impedance, loop inductance, DCIR, EM, dynamic voltage droop, current distribution, decoupling optimization, and power/ground architecture. Drive die/package co-design, including bump/BGA assignment, stack-up optimization, power/ground allocation, high-speed I/O placement, and package routing architecture. Develop simulation methodologies and automation flows for early architecture exploration, design-space optimization, and repeatable SI/PI sign-off.

5+ years of experience in signal integrity, power integrity, high-speed interconnect design, PDN design and package electrical design. Strong understanding of signal-integrity and power-integrity fundamentals, including transmission-line behavior, impedance, loss, crosstalk, return paths, power-distribution networks, inductance, decoupling, voltage droop, and current distribution. Hands-on experience with electromagnetic and SI/PI simulation tools such as Synopsys HSPICE, Ansys EDT, HFSS-PI, SIwave, Cadence Clarity, Sigrity PowerSI/PowerDC, or equivalent. Experience with package layout environments such as Cadence APD/SIP, including the ability to review and modify package structures for SI/PI optimization. Experience developing automated design optimization flows for model extraction, simulation setup, post-processing, design-space exploration, or layout optimization. Strong communication skills and the ability to work effectively across ASIC, package, PCB, system, mechanical, thermal, power, validation, and manufacturing teams.

Hands-on experience with advanced 2.5D/3D packaging, silicon or organic interposers, bridge technologies, HBM integration, IVR integration, or large-body AI/HPC packages. Experience developing early-stage SI/PI feasibility