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Principal Product Engineer - Memory IP

Cadence Design Systems

NanjingPrincipalH-1B sponsor company
Sign in to applyVerified 1h ago
Location
Nanjing
Work model
On-Site
Level
Principal
H-1B history
77 approvals (FY2023)
Posted
Aug 18, 2026

About this role

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.  Primary Responsibilities: ○ Supporting pre-silicon integration, usage, and implementation of memory subsystem products ○ Helping with internal system integration and QA testing of memory subsystem products (Controller + PHY) Analyzing and resolving complex subsystem application or implementation issues and providing professional guidance to customers ○ Supporting various memory PHY and controller SOC integration reviews and implementation reviews ○ Assisting customers with RTL and gate-level simulations to verify functionality ○ Assisting customers with timing closure and other aspects of physical integration Participating in development and refinement of product documentation and checklists for customer applications ○ Supporting post-silicon bringup and production test activities for customers as needed Enhancing customer experience by providing prompt, thorough, and technically accurate responses to customer questions ○ Leveraging AI-powered tools and assistants to enhance productivity, improve decision making, and maintain high-quality customer deliverables. ○Applying AI-powered analytics tools to extract insights, identify patterns, and generate actionable recommendations from complex datasets Position Requirements: ○ B.S Electrical/Computer Engineering (or similar degree) and 7+ years of overall experience -OR- M.S Electrical/Computer Engineering (or similar degree) and 5+ years of overall experience ○ Experience working with DDR5/4/3, LPDDR5/4/3, HBM3, GDDR6 or similar IPs ○ Verilog RTL design and gate level verification experience ○ Synthesis and static timing analysis experience (physical implementation/verification experience is a plus) ○ Familiarity with industry standard DFT flows and test methodologies. ○ Familiarity with package and board design ○ Ability to read schematics and participate in SI/PI reviews for customer board/package implementation Preferred Qualifications ○ Experience with Memory PHY and DSP based architecture ○ Experience with embedded microcontroller FW ○ Background with scripting and applying AI solutions to daily workflows   We’re doing work that matters. Help us solve what others can’t.

Listing verified 1h ago. Applications go through the company's official careers site.

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Principal Product Engineer - Memory IP at Cadence Design Systems, Nanjing | Yoinka