R&D Engineering, Principal Engineer

Descriptions & Requirements

Job Description and Requirements

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performan ce silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are passionate about advancing the boundaries of electronic design automation (EDA) and static timing analysis (STA). Combining deep domain knowledge with practical hands-on experience, you thrive in architecting complex systems that impact the global semiconductor industry. You possess a strong sense of ownership, are comfortable navigating ambiguity, and excel at resolving the most challenging technical problems. Your expertise enables you to analyze system-level tradeoffs, balancing accuracy, scalability, and performance for mission-critic al sign-off flows. You are a collaborative influencer--va lued for your ability to mentor and guide both senior and junior engineers, and for your skill in articulating architectural direction that aligns with business goals and industry trends. You are recognized for your proficiency in C/C++ and your ability to design and implement scalable, high-performan ce codebases. You are adept at identifying systemic issues and providing principled solutions, especially when working directly with customers on tapeout-critic al challenges. Your communication skills foster trust and inspire technical excellence across distributed teams. You are proactive in defining long-term strategies and have a proven track record of delivering impactful results in complex, fast-paced environments. Above all, you are driven by a desire to shape the future of silicon innovation, ensuring that the PrimeTime platform remains the industry standard for timing sign-off at advanced technology nodes. What You'll Be Doing: * Owning and evolving major architectural components of PrimeTime, including timing engines, path search frameworks, constraint modeling, and distributed/pa rallel analysis flows. * Defining long-term technical strategy for accuracy, capacity, runtime, and extensibility in static timing analysis, collaborating closely with senior R&D leadership. * Driving architectural consistency across PrimeTime, Fusion Compiler integration points, and broader sign-off ecosystems. * Leading the design and implementation of next-generatio n STA algorithms addressing m ulti-billion-c ell designs, advanced timing effects, and non-linear behaviors. * Resolving cross-cutting technical issues and making principled tradeoffs between accuracy, performance, memory footprint, and usability at sign-off. * Acting as the go-to technical authority for customer escalations, sign-off discrepancies, and complex architectural challenges. * Diagnosing systemic issues involving SDC i nterpretation, timing convergence, path pessimism/opti mism, and tool correlations across flows. * Mentoring and influencing engineers through technical reviews, discussions, and leadership--ra ising the technical bar across the organization. The Impact You Will Have: * Shape the architectural direction of PrimeTime, ensuring it remains the industry-leadi ng STA solution for advanced silicon designs. * Define how PrimeTime scales to meet the complexity and reliability demands of next-generatio n SoCs. * Reduce customer risk at tapeout by delivering architectural correctness, p redictability, and performance. * Serve as a technical pillar for a tool that is crucial to the success of global silicon innovation. * Influence the technical roadmap for sign-off methodology, driving improvements across multiple product releases. * Enhance collaboration across distributed teams, fostering a culture of technical excellence and innovation. * Directly impact customer satisfaction by