Analog Design, Sr Engineer

Descriptions & Requirements

Job Description and Requirements

Job Titles: Analog I/O Sr Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and inventive analog circuit design engineer with a deep-rooted curiosity for emerging technologies and industry-leading semiconductor processes. You thrive in dynamic, collaborative environments and are recognized for your ability to balance technical depth with practical implementation. Your expertise in I/O development, ESD (Electrostatic Discharge), and Latch-Up (LU) robustness sets you apart, and you are eager to build solutions that power the next generation of high-performance chips. You bring a strong foundation in FinFet, FDSOI, and BCD technologies, and you are excited by the prospect of owning projects end-to-end—from conceptual design through to silicon qualification. Your approach is meticulous and data-driven, ensuring each design meets the highest standards of quality and reliability. You are comfortable working across cross-functional teams, collaborating with foundries, and integrating feedback from global stakeholders. Continuous learning excites you, and you embrace opportunities to mentor others, share knowledge, and contribute to a culture of technical excellence. You are motivated by the impact your designs have on real-world products and are committed to delivering robust, scalable, and innovative solutions for Synopsys' worldwide customers.

Designing and developing best-in-class ESD and Latch-Up robust solutions for advanced interface IPs using cutting-edge FinFet, FDSOI, and BCD processes. Owning the full lifecycle of ESD structures—from schematic design, simulation, and layout to silicon qualification and production release. Leading and executing I/O development, including I/O ring design, review, and optimization for performance and robustness. Developing and qualifying Interface Testchips, ensuring comprehensive ESD and Latch-Up validation to meet global customer requirements. Running ESD simulations by building detailed ESD networks and performing advanced analyses to ensure design integrity. Applying foundry-provided PERC (Physical Verification Rule Check) rules and using PERC check tools to validate compliance and enhance design quality. Collaborating closely with foundry partners, design, and layout teams to ensure timely and effective integration of ESD and LU solutions. The Impact You Will Have: Elevating the reliability and performance of Synopsys' interface IPs, directly influencing the success of global semiconductor customers. Driving innovation in analog circuit design for next-generation silicon technologies, helping Synopsys maintain its leadership in the industry. Reducing field failures and increasing product longevity by delivering robust ESD and Latch-Up protection solutions. Accelerating time-to-market for customer products through efficient and high-quality design practices. Fostering a culture of technical excellence and continuous improvement within the analog design team. Building strong partnerships with foundries and cross-functional teams, enhancing collaboration and knowledge sharing across projects.

Proven experience in analog circuit design, with a focus on I/O development and ESD/LU robustness. Hands-on expertise with FinFet, FDSOI, and BCD process technologies from leading foundries. Strong background in ESD and Latch-Up qualification methodologies, including testchip development and validation. Proficiency in ESD simulation, ESD network construction, and use