Processor Architect

Fractile was founded in 2022 on the bet that, eventually, the world’s most capable AI systems would be limited in their impact by the time taken to produce useful outputs. We bet everything on the logical conclusion: that the only way to truly unlock this latent value, to make speed viable at scale, was to radically re-invent the hardware that we run our frontier AI models on. Ever since, we have been building chips and systems that tackle this problem: how to efficiently generate output at thousands of tokens per second, while handling the complexity and capacity challenges of operating large models at very long contexts.

The workloads that push to the limits of the current frontier are already transformational; it is the technical and economic limits on inference speed that are constraining progress. The defining work of the 21st century will be marked by the engine of inference delivering immense and diffuse chains of intellectual inquiry, in drug discovery, in software engineering, in materials discovery, in any field where progress is driven by deep reasoning and intelligence to resolve complex problems.

As Processor Architect, you'll define and drive the architecture of our core compute engines, ISA definitions and programming models through to memory hierarchies, and on-chip interconnects. This isn't just about hitting PPA targets on a spreadsheet; you'll work closely with logical design, physical design, and verification teams to translate architectural intent into working silicon that performs in the real world. Expect to be hands-on in performance modelling, detailed specification writing, bottleneck analysis, pre and post-silicon validation. You'll be the driving force behind the computational heart of our products ensuring every cycle counts and every watt is well spent.

• Define and own the compute engine architecture specifications, balancing performance, flexibility, power, area, and design complexity.

• Lead architectural exploration from early concept through to specification, coordinating with modelling, implementation, verification, and physical design teams.

• Specify execution units, memory hierarchy, instruction sets and flow — making principled trade-offs at every level.

• Help build and maintain