Analog Layout Intern

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact Marvell Central Engineering (CE) develops Marvell's most advanced high-speed SerDes (HSS) and die-to-die (D2D) IP. These IPs power AI and cloud data center infrastructure, including custom silicon (XPU and attach), switching, storage, and optical interconnect. As the engine of the company, Central Engineering provides the foundational technology behind Marvell's business units. As an Analog Layout Intern with Marvell, you'll be a member of the Central Engineering business group. You'll be part of an analog team making a big impact on this organization. Marvell has the perfect size and scale for you to learn several aspects of engineering that will be new to you, while also having the time and freedom to dive deep into the details of your specialization on most projects. What You Can Expect As an Analog Layout Intern on the AMS team, you will support the layout implementation of analog and mixed-signal integrated circuits, learning how a circuit designer's schematic becomes a physical layout that meets performance, area, and reliability requirements. Projects vary with the product cycle and your own interests, and you will be exposed to a range of IC design skills and tools. Your responsibilities will include: Learn the analog design and layout flow, and how analog layout differs from digital physical design. Create layouts for basic analog cells (for example comparators and OTAs) in advanced nodes, following analog requirements such as device matching, symmetry, shielding, and layout-dependent effects. Assist with floorplanning, placement, and routing of analog and mixed-signal blocks under the guidance of experienced engineers. Run physical verification (DRC, LVS, antenna) and help resolve issues, with support from your mentor. Learn about parasitic awareness and EM/IR considerations, and work with circuit designers to optimize the layout. Use industry-standard tools such as Cadence Virtuoso and Calibre, in a Linux environment. Meet regularly with your paired circuit designer and layout team, share progress, and document your work.

Currently pursuing a Bachelor's degree in Electronics, Electrical, or Telecommunications Engineering, Mechatronics, Computer Engineering, or a related field (expected to graduate in 2027) Basic understanding of semiconductor devices, CMOS technology, and electronic circuits. Strong passion to learn and grow expertise in analog layout. Good analytical and problem-solving skills, with attention to detail. Self-motivated, willing to learn new technologies, and able to work effectively in a team. Good English communication skills.

Coursework or projects in analog circuits, VLSI, or IC design. Familiarity with Cadence Virtuoso, Calibre DRC/LVS, or similar layout and verification tools. Basic knowledge of Linux and scripting (Python, Tcl, or SKILL). 

 Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color,