Senior Staff Engineer, Physical Design

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact Built on decades ofBuilt on decades of expertise and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you’ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, and networking applications. What You Can Expect You will work with both local and global team members on the physical design of complex chips as well as the methodology to enable an efficient and robust design process. This position also provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell. Key responsibilities include: Work with design teams across various disciplines such as Digital/RTL/Analog to ensure design convergence and integration in a timely manner. Implement/support designs with multi-voltage designs through all aspects of implementation (place and route, static timing, physical verification) using industry standard EDA tools. Work with RTL design teams to drive assembly and design closure. Provide technical direction, coaching, and mentoring to junior employees and colleagues when necessary to achieve successful project outcomes. Write scripts in Shell, Python, and TCL to extract data and achieve productivity enhancements through automation.

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 3-5 years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-3 years of experience or e quivalent professional experience in lieu of a formal degree Expertise in full-chip & sub-hierarchy integration. Experience integrating and taping out large designs utilizing a digital design environment. Good understanding of RTL to GDS flows and methodology. Good scripting skills in Perl, tcl and Python. Good understanding of digital logic and computer architecture Knowledge of Verilog. Good communication skills and self-discipline contributing in a team environment. Experience with multi-voltage and low-power design techniques is a plus. Experience with Cadence Innovus is preferred.   Expected Base Pay Range (USD) 112,300 - 166,280, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. 
This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.
 Additional Compensation and Benefit Elements   Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock